From 53847a211bd78a9cbf838f63f155368c641f7cd5 Mon Sep 17 00:00:00 2001 From: Daniele Forsi Date: Tue, 22 Jul 2014 18:00:56 +0200 Subject: src/.../Kconfig: various small fixes to texts Fixed spelling and added empty lines to separate the help from the text automatically added during make menuconfig. Change-Id: I6eee2c86e30573deb8cf0d42fda8b8329e1156c7 Signed-off-by: Daniele Forsi Reviewed-on: http://review.coreboot.org/6313 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan --- src/soc/intel/baytrail/Kconfig | 2 +- src/soc/intel/fsp_baytrail/Kconfig | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'src/soc/intel') diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index a93b487b87..a6a3a44cfa 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -148,7 +148,7 @@ config DCACHE_RAM_ROMSTAGE_STACK_SIZE default 0x800 help The amount of anticipated stack usage from the data cache - during pre-ram rom stage execution. + during pre-RAM ROM stage execution. config RESET_ON_INVALID_RAMSTAGE_CACHE bool "Reset the system on S3 wake when ramstage cache invalid." diff --git a/src/soc/intel/fsp_baytrail/Kconfig b/src/soc/intel/fsp_baytrail/Kconfig index 312449ee67..cb4757bca3 100644 --- a/src/soc/intel/fsp_baytrail/Kconfig +++ b/src/soc/intel/fsp_baytrail/Kconfig @@ -78,7 +78,7 @@ config VGA_BIOS_ID default "8086,0f31" help This is the default PCI ID for the Bay Trail graphics - devices. This string names the vbios rom in cbfs. + devices. This string names the vbios ROM in cbfs. config INCLUDE_MICROCODE_IN_BUILD bool "Build in microcode patch" -- cgit v1.2.3