From 4a69c34d54d587ba00c6c8e4f9056596014a7541 Mon Sep 17 00:00:00 2001 From: Lee Leahy Date: Thu, 20 Nov 2014 16:56:44 -0800 Subject: Broadwell: Pass TSC value to romstage_main The romstage_main routine takes three parameters: bist, tsc_low and tsc_hi. However in cache_as_ram.inc only the bist value is being passed. This patch adds the two halves of the TSC value. BRANCH=none BUG=None TEST=Build and run on Samus Change-Id: I3d216edd0be65f29b51a66ed67b2d17910a594d4 Signed-off-by: Stefan Reinauer Original-Commit-Id: de565f28dce8a549d74defbcf5eaf8116bb1b831 Original-Signed-off-by: Lee Leahy Original-Change-Id: I34fb21e493dcb3a44426ba7964cd72a319a4254e Original-Reviewed-on: https://chromium-review.googlesource.com/231173 Original-Reviewed-by: Duncan Laurie Reviewed-on: http://review.coreboot.org/9280 Reviewed-by: Paul Menzel Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/soc/intel/broadwell/romstage/cache_as_ram.inc | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'src/soc/intel') diff --git a/src/soc/intel/broadwell/romstage/cache_as_ram.inc b/src/soc/intel/broadwell/romstage/cache_as_ram.inc index 4e6cf09f72..a10ca4ca1b 100644 --- a/src/soc/intel/broadwell/romstage/cache_as_ram.inc +++ b/src/soc/intel/broadwell/romstage/cache_as_ram.inc @@ -180,7 +180,13 @@ clear_mtrrs: /* Restore the BIST result. */ movl %ebp, %eax + + /* Build the call frame. */ movl %esp, %ebp + movd %mm1, %ebx + pushl %ebx + movd %mm0, %ebx + pushl %ebx pushl %eax before_romstage: -- cgit v1.2.3