From 4a47e4b8eedafa3f2099393de1f00365d1846ee5 Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Tue, 9 May 2017 16:14:36 +0200 Subject: soc/intel/skylake/chip.h: Reorder declarations MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Place `tdp_pl2_override` above the FSP options as it's not an FSP option. Change-Id: Idff2b628d19ce1a80294b28c55c05ba4157d07e0 Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/19637 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Stefan Reinauer --- src/soc/intel/skylake/chip.h | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'src/soc/intel') diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index 88d598f9a8..b4f6545c36 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -94,6 +94,9 @@ struct soc_intel_skylake_config { /* TCC activation offset */ int tcc_offset; + /* PL2 Override value in Watts */ + u32 tdp_pl2_override; + /* * The following fields come from FspUpdVpd.h. * These are configuration values that are passed to FSP during @@ -392,8 +395,6 @@ struct soc_intel_skylake_config { * Setting to 0 (default) disables Heci1 and hides the device from OS */ u8 HeciEnabled; - /* PL2 Override value in Watts */ - u32 tdp_pl2_override; u8 PmTimerDisabled; /* Intel Speed Shift Technology */ u8 speed_shift_enable; -- cgit v1.2.3