From 491c016d77fa56461e8669e45796da97bbab3c37 Mon Sep 17 00:00:00 2001
From: Andrey Petrov <andrey.petrov@intel.com>
Date: Wed, 2 Mar 2016 15:09:27 -0800
Subject: soc/intel/apollolake: Add cbmem_top() implementation

On Apollolake CPU memory mapping is similar to previous SoC, and
we place CBMEM right under TSEG.

Change-Id: I606f690449ba98af6e9fc3074d677c7287892164
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/13883
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
---
 src/soc/intel/apollolake/Makefile.inc   |  2 ++
 src/soc/intel/apollolake/memmap.c       | 27 +++++++++++++++++++++++++++
 src/soc/intel/apollolake/placeholders.c |  5 -----
 3 files changed, 29 insertions(+), 5 deletions(-)
 create mode 100644 src/soc/intel/apollolake/memmap.c

(limited to 'src/soc/intel')

diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc
index 81ca688d67..dd2213e869 100644
--- a/src/soc/intel/apollolake/Makefile.inc
+++ b/src/soc/intel/apollolake/Makefile.inc
@@ -20,12 +20,14 @@ romstage-y += placeholders.c
 romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += romstage.c
 romstage-y += gpio.c
 romstage-$(CONFIG_SOC_UART_DEBUG) += uart_early.c
+romstage-y += memmap.c
 romstage-y += mmap_boot.c
 
 smm-y += placeholders.c
 ramstage-y += placeholders.c
 ramstage-y += gpio.c
 ramstage-$(CONFIG_SOC_UART_DEBUG) += uart_early.c
+ramstage-y += memmap.c
 ramstage-y += mmap_boot.c
 
 CPPFLAGS_common += -I$(src)/soc/intel/apollolake/include
diff --git a/src/soc/intel/apollolake/memmap.c b/src/soc/intel/apollolake/memmap.c
new file mode 100644
index 0000000000..bfff9652da
--- /dev/null
+++ b/src/soc/intel/apollolake/memmap.c
@@ -0,0 +1,27 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Intel Corp.
+ * (Written by Andrey Petrov <andrey.petrov@intel.com> for Intel Corp.)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <arch/io.h>
+#include <cbmem.h>
+#include <device/pci.h>
+#include <soc/northbridge.h>
+#include <soc/pci_devs.h>
+
+static uintptr_t smm_region_start(void)
+{
+	return ALIGN_DOWN(pci_read_config32(NB_DEV_ROOT, TSEG), 1*MiB);
+}
+
+void *cbmem_top(void)
+{
+	return (void *)smm_region_start();
+}
diff --git a/src/soc/intel/apollolake/placeholders.c b/src/soc/intel/apollolake/placeholders.c
index 3a818eb1e3..808bd5490b 100644
--- a/src/soc/intel/apollolake/placeholders.c
+++ b/src/soc/intel/apollolake/placeholders.c
@@ -3,11 +3,6 @@
 #include <delay.h>
 #include <rules.h>
 
-void *cbmem_top(void)
-{
-	return NULL;
-}
-
 void southbridge_smi_set_eos(void)
 {
 }
-- 
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