From 4288cda2ed8a765c53a3823b4e9a53d93d78a490 Mon Sep 17 00:00:00 2001 From: Meera Ravindranath Date: Fri, 19 Jul 2019 15:32:29 +0530 Subject: soc/intel/common: Set controller state to active in GSPI init Set the controller state to D0 during the GSPI sequence,this ensures the controller is up and active. BUG=b:135941367 TEST=Verify no timeouts seen during GSPI controller enumeration sequence for CML and ICL platforms. Signed-off-by: Meera Ravindranath Change-Id: I2f95059453ca5565a38650b147590ece4d8bf5ed Reviewed-on: https://review.coreboot.org/c/coreboot/+/34449 Tested-by: build bot (Jenkins) Reviewed-by: Subrata Banik Reviewed-by: Furquan Shaikh Reviewed-by: Aamir Bohra --- src/soc/intel/common/block/gspi/gspi.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) (limited to 'src/soc/intel') diff --git a/src/soc/intel/common/block/gspi/gspi.c b/src/soc/intel/common/block/gspi/gspi.c index 17532bf6db..beb12fb231 100644 --- a/src/soc/intel/common/block/gspi/gspi.c +++ b/src/soc/intel/common/block/gspi/gspi.c @@ -23,6 +23,7 @@ #include #include #include +#include #include #include #include @@ -446,8 +447,19 @@ static uint32_t gspi_get_clk_div(unsigned int gspi_bus) static int gspi_ctrlr_setup(const struct spi_slave *dev) { struct spi_cfg cfg; + int devfn; uint32_t cs_ctrl, sscr0, sscr1, clocks, sitf, sirf, pol; struct gspi_ctrlr_params params, *p = ¶ms; + const struct device *device; + + devfn = gspi_soc_bus_to_devfn(dev->bus); + if (devfn < 0) { + printk(BIOS_ERR, "%s: No GSPI controller found on SPI bus %u.\n", + __func__, dev->bus); + return -1; + } + + device = pcidev_path_on_root(devfn); /* Only chip select 0 is supported. */ if (dev->cs != 0) { @@ -466,6 +478,9 @@ static int gspi_ctrlr_setup(const struct spi_slave *dev) return -1; } + /* Ensure controller is in D0 state */ + lpss_set_power_state(device, STATE_D0); + /* Take controller out of reset, keeping DMA in reset. */ gspi_write_mmio_reg(p, RESETS, CTRLR_ACTIVE | DMA_RESET); -- cgit v1.2.3