From 330dc10cfd956df91855593b6f33b502c6883c55 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Thu, 9 Nov 2017 15:00:54 +0530 Subject: soc/intel/apollolake: Include HECI BAR0 address inside iomap.h This ensures HECI1_BASE_ADDRESS macro is coming from respective SoC dirctory and not hardcoded inside common cse code. As per firmware specification HECI1_BASE_ADDRESS might be different between different socs. Change-Id: I502b5b41b449bb07f14f07435bf311bbd4f943b6 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/22393 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin Reviewed-by: Furquan Shaikh --- src/soc/intel/apollolake/include/soc/iomap.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'src/soc/intel') diff --git a/src/soc/intel/apollolake/include/soc/iomap.h b/src/soc/intel/apollolake/include/soc/iomap.h index c3eb66bef6..d4cd0952e8 100644 --- a/src/soc/intel/apollolake/include/soc/iomap.h +++ b/src/soc/intel/apollolake/include/soc/iomap.h @@ -44,6 +44,8 @@ #define SRAM_BASE_2 0xfe902000 #define SRAM_SIZE_2 (4 * KiB) +#define HECI1_BASE_ADDRESS 0xfed1a000 + /* Temporary BAR for SPI until PCI enumeration assigns a BAR in ramstage. */ #define PRERAM_SPI_BASE_ADDRESS 0xfe010000 -- cgit v1.2.3