From 32d47eb688390d08e0f3f839df69371b55af8889 Mon Sep 17 00:00:00 2001 From: Kyösti Mälkki Date: Sat, 28 Sep 2019 00:00:30 +0300 Subject: soc/intel: Rename MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The filename chip.h has a special purpose with the generation of static devicetree, where the configuration structure name matches the path to the chip.h file. For example, soc/intel/skylake/chip.h defines struct soc_intel_skylake_config. The renamed file did not follow this convention and the structure it defines would conflict with one defined soc/intel/common/chip.h if such is ever added. Change-Id: Id3d56bf092c6111d2293136865b053b095e92d6b Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/35657 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin Reviewed-by: Furquan Shaikh --- src/soc/intel/apollolake/chip.c | 2 +- src/soc/intel/apollolake/chip.h | 2 +- src/soc/intel/cannonlake/chip.c | 2 +- src/soc/intel/cannonlake/chip.h | 2 +- src/soc/intel/cannonlake/lockdown.c | 2 +- src/soc/intel/cannonlake/romstage/romstage.c | 2 +- src/soc/intel/common/block/cpu/mp_init.c | 2 +- src/soc/intel/common/block/gspi/gspi.c | 2 +- src/soc/intel/common/block/i2c/i2c.c | 2 +- .../intel/common/block/include/intelblocks/cfg.h | 45 ++++++++++++++++++++++ .../intel/common/block/include/intelblocks/chip.h | 45 ---------------------- src/soc/intel/common/block/scs/mmc.c | 2 +- src/soc/intel/common/block/thermal/thermal.c | 2 +- src/soc/intel/common/pch/lockdown/lockdown.c | 2 +- src/soc/intel/icelake/chip.c | 2 +- src/soc/intel/icelake/chip.h | 2 +- src/soc/intel/icelake/lockdown.c | 2 +- src/soc/intel/icelake/romstage/romstage.c | 2 +- src/soc/intel/skylake/chip.c | 2 +- src/soc/intel/skylake/chip.h | 2 +- src/soc/intel/skylake/chip_fsp20.c | 2 +- src/soc/intel/skylake/i2c.c | 2 +- src/soc/intel/skylake/lockdown.c | 2 +- 23 files changed, 66 insertions(+), 66 deletions(-) create mode 100644 src/soc/intel/common/block/include/intelblocks/cfg.h delete mode 100644 src/soc/intel/common/block/include/intelblocks/chip.h (limited to 'src/soc/intel') diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index b69f9eeeef..b7159efaec 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -28,7 +28,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h index b9e368cddc..85cfff9af5 100644 --- a/src/soc/intel/apollolake/chip.h +++ b/src/soc/intel/apollolake/chip.h @@ -20,7 +20,7 @@ #define _SOC_APOLLOLAKE_CHIP_H_ #include -#include +#include #include #include #include diff --git a/src/soc/intel/cannonlake/chip.c b/src/soc/intel/cannonlake/chip.c index 4e0dba5cea..c0810fb2ea 100644 --- a/src/soc/intel/cannonlake/chip.c +++ b/src/soc/intel/cannonlake/chip.c @@ -18,7 +18,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index 451c920fae..b937699c3c 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -18,7 +18,7 @@ #ifndef _SOC_CHIP_H_ #define _SOC_CHIP_H_ -#include +#include #include #include #include diff --git a/src/soc/intel/cannonlake/lockdown.c b/src/soc/intel/cannonlake/lockdown.c index e2fcc3a46e..ba68aa385c 100644 --- a/src/soc/intel/cannonlake/lockdown.c +++ b/src/soc/intel/cannonlake/lockdown.c @@ -14,7 +14,7 @@ */ #include -#include +#include #include #include diff --git a/src/soc/intel/cannonlake/romstage/romstage.c b/src/soc/intel/cannonlake/romstage/romstage.c index ba583b9a6e..f782f63622 100644 --- a/src/soc/intel/cannonlake/romstage/romstage.c +++ b/src/soc/intel/cannonlake/romstage/romstage.c @@ -17,7 +17,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/src/soc/intel/common/block/cpu/mp_init.c b/src/soc/intel/common/block/cpu/mp_init.c index e0cee1771e..2c5061f1d6 100644 --- a/src/soc/intel/common/block/cpu/mp_init.c +++ b/src/soc/intel/common/block/cpu/mp_init.c @@ -21,7 +21,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/src/soc/intel/common/block/gspi/gspi.c b/src/soc/intel/common/block/gspi/gspi.c index f937bd6eed..33f376ee77 100644 --- a/src/soc/intel/common/block/gspi/gspi.c +++ b/src/soc/intel/common/block/gspi/gspi.c @@ -21,7 +21,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/src/soc/intel/common/block/i2c/i2c.c b/src/soc/intel/common/block/i2c/i2c.c index 854a61a884..fb7aea2c17 100644 --- a/src/soc/intel/common/block/i2c/i2c.c +++ b/src/soc/intel/common/block/i2c/i2c.c @@ -21,7 +21,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/src/soc/intel/common/block/include/intelblocks/cfg.h b/src/soc/intel/common/block/include/intelblocks/cfg.h new file mode 100644 index 0000000000..e7e381bfe4 --- /dev/null +++ b/src/soc/intel/common/block/include/intelblocks/cfg.h @@ -0,0 +1,45 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef SOC_INTEL_COMMON_BLOCK_CFG_H +#define SOC_INTEL_COMMON_BLOCK_CFG_H + +#include +#include +#include + +enum { + CHIPSET_LOCKDOWN_FSP = 0, /* FSP handles locking per UPDs */ + CHIPSET_LOCKDOWN_COREBOOT, /* coreboot handles locking */ +}; + +/* + * This structure will hold data required by common blocks. + * These are soc specific configurations which will be filled by soc. + * We'll fill this structure once during init and use the data in common block. + */ +struct soc_intel_common_config { + int chipset_lockdown; + struct gspi_cfg gspi[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX]; + struct dw_i2c_bus_config i2c[CONFIG_SOC_INTEL_I2C_DEV_MAX]; + /* PCH Thermal Trip Temperature in deg C */ + uint8_t pch_thermal_trip; + struct mmc_dll_params emmc_dll; +}; + +/* This function to retrieve soc config structure required by common code */ +const struct soc_intel_common_config *chip_get_common_soc_structure(void); + +#endif /* SOC_INTEL_COMMON_BLOCK_CFG_H */ diff --git a/src/soc/intel/common/block/include/intelblocks/chip.h b/src/soc/intel/common/block/include/intelblocks/chip.h deleted file mode 100644 index 1e830d5d17..0000000000 --- a/src/soc/intel/common/block/include/intelblocks/chip.h +++ /dev/null @@ -1,45 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2018 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - */ - -#ifndef SOC_INTEL_COMMON_BLOCK_CHIP_H -#define SOC_INTEL_COMMON_BLOCK_CHIP_H - -#include -#include -#include - -enum { - CHIPSET_LOCKDOWN_FSP = 0, /* FSP handles locking per UPDs */ - CHIPSET_LOCKDOWN_COREBOOT, /* coreboot handles locking */ -}; - -/* - * This structure will hold data required by common blocks. - * These are soc specific configurations which will be filled by soc. - * We'll fill this structure once during init and use the data in common block. - */ -struct soc_intel_common_config { - int chipset_lockdown; - struct gspi_cfg gspi[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX]; - struct dw_i2c_bus_config i2c[CONFIG_SOC_INTEL_I2C_DEV_MAX]; - /* PCH Thermal Trip Temperature in deg C */ - uint8_t pch_thermal_trip; - struct mmc_dll_params emmc_dll; -}; - -/* This function to retrieve soc config structure required by common code */ -const struct soc_intel_common_config *chip_get_common_soc_structure(void); - -#endif /* SOC_INTEL_COMMON_BLOCK_CHIP_H */ diff --git a/src/soc/intel/common/block/scs/mmc.c b/src/soc/intel/common/block/scs/mmc.c index 5b2e2c7d33..4ff3ac5e7e 100644 --- a/src/soc/intel/common/block/scs/mmc.c +++ b/src/soc/intel/common/block/scs/mmc.c @@ -16,7 +16,7 @@ #include #include #include -#include +#include #include static int mmc_write_dll_reg(void *bar, uint32_t reg, uint32_t val) diff --git a/src/soc/intel/common/block/thermal/thermal.c b/src/soc/intel/common/block/thermal/thermal.c index 39a98a41d8..8f2fd49da2 100644 --- a/src/soc/intel/common/block/thermal/thermal.c +++ b/src/soc/intel/common/block/thermal/thermal.c @@ -15,7 +15,7 @@ #include #include -#include +#include #include #include diff --git a/src/soc/intel/common/pch/lockdown/lockdown.c b/src/soc/intel/common/pch/lockdown/lockdown.c index 99d8a35ea7..4a3209e03e 100644 --- a/src/soc/intel/common/pch/lockdown/lockdown.c +++ b/src/soc/intel/common/pch/lockdown/lockdown.c @@ -14,7 +14,7 @@ */ #include -#include +#include #include #include #include diff --git a/src/soc/intel/icelake/chip.c b/src/soc/intel/icelake/chip.c index c4abb0c3f7..e71c573f98 100644 --- a/src/soc/intel/icelake/chip.c +++ b/src/soc/intel/icelake/chip.c @@ -18,7 +18,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/src/soc/intel/icelake/chip.h b/src/soc/intel/icelake/chip.h index 72596c46e2..fc9341c58b 100644 --- a/src/soc/intel/icelake/chip.h +++ b/src/soc/intel/icelake/chip.h @@ -16,7 +16,7 @@ #ifndef _SOC_CHIP_H_ #define _SOC_CHIP_H_ -#include +#include #include #include #include diff --git a/src/soc/intel/icelake/lockdown.c b/src/soc/intel/icelake/lockdown.c index 8fa5e154f2..85a93c7c8e 100644 --- a/src/soc/intel/icelake/lockdown.c +++ b/src/soc/intel/icelake/lockdown.c @@ -14,7 +14,7 @@ */ #include -#include +#include #include #include diff --git a/src/soc/intel/icelake/romstage/romstage.c b/src/soc/intel/icelake/romstage/romstage.c index 3d21a45e33..2c4ba67e04 100644 --- a/src/soc/intel/icelake/romstage/romstage.c +++ b/src/soc/intel/icelake/romstage/romstage.c @@ -17,7 +17,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index 212c24467e..ddb29327a1 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -19,7 +19,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index fee14d8d7e..70fb045baf 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -22,7 +22,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c index d1d7d6f50a..e46e52ccd2 100644 --- a/src/soc/intel/skylake/chip_fsp20.c +++ b/src/soc/intel/skylake/chip_fsp20.c @@ -23,7 +23,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/src/soc/intel/skylake/i2c.c b/src/soc/intel/skylake/i2c.c index 9fd9bf39e6..316c633c4d 100644 --- a/src/soc/intel/skylake/i2c.c +++ b/src/soc/intel/skylake/i2c.c @@ -15,7 +15,7 @@ */ #include -#include +#include #include #include diff --git a/src/soc/intel/skylake/lockdown.c b/src/soc/intel/skylake/lockdown.c index 864cefe0b9..69459e7e03 100644 --- a/src/soc/intel/skylake/lockdown.c +++ b/src/soc/intel/skylake/lockdown.c @@ -14,7 +14,7 @@ */ #include -#include +#include #include #include #include -- cgit v1.2.3