From 3299b2ded5327cd4a40e68554a8c2fd227355ada Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Thu, 6 Aug 2020 07:54:37 +0200 Subject: soc/intel/tigerlake: Add IRQs for LPSS uart Values are taken from pci_irqs.asl. The common code will make use of those defines to generate ACPI SSDT code for LPSS uarts operating in "ACPI mode". Change-Id: I5ef93493965834cda30d70918e65de3129e547b7 Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/c/coreboot/+/44260 Reviewed-by: Christian Walter Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/soc/intel/tigerlake/include/soc/irq.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'src/soc/intel') diff --git a/src/soc/intel/tigerlake/include/soc/irq.h b/src/soc/intel/tigerlake/include/soc/irq.h index ad70290148..f95f9f672c 100644 --- a/src/soc/intel/tigerlake/include/soc/irq.h +++ b/src/soc/intel/tigerlake/include/soc/irq.h @@ -9,4 +9,8 @@ #define PCH_IRQ10 10 #define PCH_IRQ11 11 +#define LPSS_UART0_IRQ 16 +#define LPSS_UART1_IRQ 17 +#define LPSS_UART2_IRQ 33 + #endif /* _SOC_IRQ_H_ */ -- cgit v1.2.3