From 305b6488e4cd4adfc7427938928dca51f4d70dd7 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Sun, 22 Sep 2019 21:56:17 +0200 Subject: soc/intel/cannonlake: set MSR LT_LOCK_MEMORY at end of POST MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit FSP does not set the MSR LT_LOCK_MEMORY when SkipMpInit=1. Therefore, set LT_LOCK_MEMORY at end of POST, when native MP init is used, to protect SMM in accordance to Intel BWG. Test on clevo/cml-u: chipsec says LT_LOCK_MEMORY is locked. Change-Id: Iaadd4996653c4f27d268b1c4773c1e2e86114912 Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/36356 Reviewed-by: Angel Pons Reviewed-by: Tim Wawrzynczak Tested-by: build bot (Jenkins) --- src/soc/intel/cannonlake/finalize.c | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'src/soc/intel') diff --git a/src/soc/intel/cannonlake/finalize.c b/src/soc/intel/cannonlake/finalize.c index 8387bb86f7..9b56c0ada2 100644 --- a/src/soc/intel/cannonlake/finalize.c +++ b/src/soc/intel/cannonlake/finalize.c @@ -6,6 +6,7 @@ #include #include #include +#include #include #include #include @@ -69,6 +70,14 @@ static void pch_finalize(void) pch_handle_sideband(config); pmc_clear_pmcon_sts(); + + /* + * Lock chipset memory registers to protect SMM. + * When SkipMpInit=0, this is done by FSP. + */ + if (!CONFIG(USE_INTEL_FSP_MP_INIT)) + cpu_lt_lock_memory(); + } static void soc_finalize(void *unused) -- cgit v1.2.3