From 2c7842407af8e84b28d41e8369ccf199748f65ce Mon Sep 17 00:00:00 2001 From: John Zhao Date: Tue, 16 Feb 2021 09:22:47 -0800 Subject: soc/intel/tigerlake: Remove polling for Link Active Status at resume Tigerlake TBT only has SW CM support. The polling for "LA == 1" is not applicable for SW CM platform at the resume sequence. This change removes the pollng for "LA == 1" to improve resume performance. BUG=b:177519081 TEST=Boot to kernel and validated s0ix on Voxel board. Signed-off-by: John Zhao Change-Id: I886001f71bf893dc7eda98403fa4e1a3de6b958e Reviewed-on: https://review.coreboot.org/c/coreboot/+/50806 Tested-by: build bot (Jenkins) Reviewed-by: Sukumar Ghorai Reviewed-by: Tim Wawrzynczak --- src/soc/intel/tigerlake/acpi/tcss_pcierp.asl | 12 ------------ 1 file changed, 12 deletions(-) (limited to 'src/soc/intel') diff --git a/src/soc/intel/tigerlake/acpi/tcss_pcierp.asl b/src/soc/intel/tigerlake/acpi/tcss_pcierp.asl index 39180f7393..0453f1c7d4 100644 --- a/src/soc/intel/tigerlake/acpi/tcss_pcierp.asl +++ b/src/soc/intel/tigerlake/acpi/tcss_pcierp.asl @@ -144,18 +144,6 @@ Method (D3CX, 0, Serialized) Local1 = L23R } STAT = 0x1 - - /* Wait for LA = 1 */ - Local0 = 0 - Local1 = LASX - While (Local1 == 0) { - If (Local0 > 20) { - Break - } - Sleep(5) - Local0++ - Local1 = LASX - } } /* -- cgit v1.2.3