From 2a12e2e8da2477d97b8774babd1a74dda65d11a0 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Mon, 25 Jul 2016 11:48:03 -0700 Subject: vboot: Separate vboot from chromeos VBOOT_VERIFY_FIRMWARE should be independent of CHROMEOS. This allows use of verified boot library without having to stick to CHROMEOS. BUG=chrome-os-partner:55639 Change-Id: Ia2c328712caedd230ab295b8a613e3c1ed1532d9 Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/15867 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie --- src/soc/intel/apollolake/Kconfig | 4 ++-- src/soc/intel/apollolake/lpc.c | 4 ++-- src/soc/intel/apollolake/pmutil.c | 2 +- src/soc/intel/broadwell/igd.c | 2 +- src/soc/intel/broadwell/lpc.c | 13 +++++-------- src/soc/intel/skylake/Kconfig | 4 ++-- src/soc/intel/skylake/igd.c | 3 ++- src/soc/intel/skylake/pmc.c | 12 +++++------- src/soc/intel/skylake/romstage/power_state.c | 2 +- 9 files changed, 21 insertions(+), 25 deletions(-) (limited to 'src/soc/intel') diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 3f14880477..07456795b5 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -59,13 +59,13 @@ config CPU_SPECIFIC_OPTIONS config CHROMEOS select CHROMEOS_RAMOOPS_DYNAMIC - select CHROMEOS_VBNV_CMOS - select CHROMEOS_VBNV_CMOS_BACKUP_TO_FLASH select EC_SOFTWARE_SYNC if EC_GOOGLE_CHROMEEC select SEPARATE_VERSTAGE select VBOOT_OPROM_MATTERS select VBOOT_SAVE_RECOVERY_REASON_ON_REBOOT select VBOOT_STARTS_IN_BOOTBLOCK + select VBOOT_VBNV_CMOS + select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH select VIRTUAL_DEV_SWITCH config TPM_ON_FAST_SPI diff --git a/src/soc/intel/apollolake/lpc.c b/src/soc/intel/apollolake/lpc.c index cc4de886e3..5455dedf1d 100644 --- a/src/soc/intel/apollolake/lpc.c +++ b/src/soc/intel/apollolake/lpc.c @@ -25,7 +25,7 @@ #include #include #include -#include +#include #include "chip.h" @@ -60,7 +60,7 @@ static void rtc_init(void) rtc_fail = !!(ps->gen_pmcon1 & RPS); /* Ensure the date is set including century byte. */ cmos_check_update_date(); - if (IS_ENABLED(CONFIG_CHROMEOS_VBNV_CMOS)) + if (IS_ENABLED(CONFIG_VBOOT_VBNV_CMOS)) init_vbnv_cmos(rtc_fail); else cmos_init(rtc_fail); diff --git a/src/soc/intel/apollolake/pmutil.c b/src/soc/intel/apollolake/pmutil.c index e23feb2109..61aa6375d3 100644 --- a/src/soc/intel/apollolake/pmutil.c +++ b/src/soc/intel/apollolake/pmutil.c @@ -27,7 +27,7 @@ #include #include #include -#include +#include static uintptr_t read_pmc_mmio_bar(void) { diff --git a/src/soc/intel/broadwell/igd.c b/src/soc/intel/broadwell/igd.c index 599a95c9d8..d25ddcc547 100644 --- a/src/soc/intel/broadwell/igd.c +++ b/src/soc/intel/broadwell/igd.c @@ -30,7 +30,7 @@ #include #include #include -#include +#include #define GT_RETRY 1000 #define GT_CDCLK_337 0 diff --git a/src/soc/intel/broadwell/lpc.c b/src/soc/intel/broadwell/lpc.c index 7e57b23504..20fa345676 100644 --- a/src/soc/intel/broadwell/lpc.c +++ b/src/soc/intel/broadwell/lpc.c @@ -44,11 +44,8 @@ #include #include #include - -#if IS_ENABLED(CONFIG_CHROMEOS) -#include -#include -#endif +#include +#include static void pch_enable_ioapic(struct device *dev) { @@ -175,14 +172,14 @@ static void pch_power_options(device_t dev) enable_alt_smi(config->alt_gp_smi_en); } -#if IS_ENABLED(CONFIG_CHROMEOS) && IS_ENABLED(CONFIG_CHROMEOS_VBNV_CMOS) +#if IS_ENABLED(CONFIG_CHROMEOS) && IS_ENABLED(CONFIG_VBOOT_VBNV_CMOS) /* * Preserve Vboot NV data when clearing CMOS as it will * have been re-initialized already by Vboot firmware init. */ static void pch_cmos_init_preserve(int reset) { - uint8_t vbnv[VBNV_BLOCK_SIZE]; + uint8_t vbnv[VBOOT_VBNV_BLOCK_SIZE]; if (reset) read_vbnv(vbnv); @@ -207,7 +204,7 @@ static void pch_rtc_init(struct device *dev) printk(BIOS_DEBUG, "rtc_failed = 0x%x\n", rtc_failed); } -#if IS_ENABLED(CONFIG_CHROMEOS) && IS_ENABLED(CONFIG_CHROMEOS_VBNV_CMOS) +#if IS_ENABLED(CONFIG_CHROMEOS) && IS_ENABLED(CONFIG_VBOOT_VBNV_CMOS) pch_cmos_init_preserve(rtc_failed); #else cmos_init(rtc_failed); diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 4c055ea1df..b86d002bc2 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -53,12 +53,12 @@ config CPU_SPECIFIC_OPTIONS config CHROMEOS select CHROMEOS_RAMOOPS_DYNAMIC - select CHROMEOS_VBNV_CMOS - select CHROMEOS_VBNV_CMOS_BACKUP_TO_FLASH select EC_SOFTWARE_SYNC if EC_GOOGLE_CHROMEEC select VBOOT_EC_SLOW_UPDATE select VBOOT_OPROM_MATTERS select VBOOT_SAVE_RECOVERY_REASON_ON_REBOOT + select VBOOT_VBNV_CMOS + select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH select VIRTUAL_DEV_SWITCH config BOOTBLOCK_CPU_INIT diff --git a/src/soc/intel/skylake/igd.c b/src/soc/intel/skylake/igd.c index 4bb597c64c..209d22c8cf 100644 --- a/src/soc/intel/skylake/igd.c +++ b/src/soc/intel/skylake/igd.c @@ -16,6 +16,7 @@ #include #include +#include #include #include #include @@ -31,7 +32,7 @@ #include #include #include -#include +#include u32 map_oprom_vendev(u32 vendev) { diff --git a/src/soc/intel/skylake/pmc.c b/src/soc/intel/skylake/pmc.c index 6b7a17b6a9..a8ec7b6a8e 100644 --- a/src/soc/intel/skylake/pmc.c +++ b/src/soc/intel/skylake/pmc.c @@ -35,10 +35,8 @@ #include #include #include -#if IS_ENABLED(CONFIG_CHROMEOS) -#include -#include -#endif +#include +#include static const struct reg_script pch_pmc_misc_init_script[] = { /* SLP_S4=4s, SLP_S3=50ms, disable SLP_X stretching after SUS loss. */ @@ -108,14 +106,14 @@ static void pch_set_acpi_mode(void) } } -#if IS_ENABLED(CONFIG_CHROMEOS_VBNV_CMOS) +#if IS_ENABLED(CONFIG_VBOOT_VBNV_CMOS) /* * Preserve Vboot NV data when clearing CMOS as it will * have been re-initialized already by Vboot firmware init. */ static void pch_cmos_init_preserve(int reset) { - uint8_t vbnv[VBNV_BLOCK_SIZE]; + uint8_t vbnv[VBOOT_VBNV_BLOCK_SIZE]; if (reset) read_vbnv(vbnv); @@ -143,7 +141,7 @@ static void pch_rtc_init(void) /* Ensure the date is set including century byte. */ cmos_check_update_date(); -#if IS_ENABLED(CONFIG_CHROMEOS_VBNV_CMOS) +#if IS_ENABLED(CONFIG_VBOOT_VBNV_CMOS) pch_cmos_init_preserve(rtc_failed); #else cmos_init(rtc_failed); diff --git a/src/soc/intel/skylake/romstage/power_state.c b/src/soc/intel/skylake/romstage/power_state.c index 209beebe0f..cf75ccb750 100644 --- a/src/soc/intel/skylake/romstage/power_state.c +++ b/src/soc/intel/skylake/romstage/power_state.c @@ -30,7 +30,7 @@ #include #include #include -#include +#include static struct chipset_power_state power_state CAR_GLOBAL; -- cgit v1.2.3