From 2837cf81820308e50a06fce60d49cca9eb77ff25 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Mon, 12 Jul 2021 11:09:55 +0200 Subject: soc/intel/skylake: Rename `Rmt` devicetree setting MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Rename `Rmt` to `RMT` for consistency with the UPD name. Change-Id: I905b9b65fa6c5711c6e726cc09d3cad5ba3640a1 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/56206 Tested-by: build bot (Jenkins) Reviewed-by: Felix Singer Reviewed-by: Michael Niewöhner --- src/soc/intel/skylake/chip.h | 2 +- src/soc/intel/skylake/romstage/fsp_params.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'src/soc/intel') diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index d30547ec26..59f75bf353 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -94,7 +94,7 @@ struct soc_intel_skylake_config { } SaGv; /* Enable/disable Rank Margin Tool */ - u8 Rmt; + u8 RMT; /* Disable Command TriState */ u8 CmdTriStateDis; diff --git a/src/soc/intel/skylake/romstage/fsp_params.c b/src/soc/intel/skylake/romstage/fsp_params.c index f05532c416..21526e4848 100644 --- a/src/soc/intel/skylake/romstage/fsp_params.c +++ b/src/soc/intel/skylake/romstage/fsp_params.c @@ -83,7 +83,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, m_cfg->ProbelessTrace = 0; m_cfg->SaGv = config->SaGv; m_cfg->UserBd = BOARD_TYPE_ULT_ULX; - m_cfg->RMT = config->Rmt; + m_cfg->RMT = config->RMT; m_cfg->CmdTriStateDis = config->CmdTriStateDis; m_cfg->DdrFreqLimit = 0; m_cfg->VmxEnable = CONFIG(ENABLE_VMX); -- cgit v1.2.3