From 21df67ecd467c82f87ac80a658522c3fbf70a144 Mon Sep 17 00:00:00 2001 From: Caveh Jalali Date: Thu, 8 Mar 2018 17:58:21 -0800 Subject: soc/intel/cannonlake: Disable RTC write protect The cannonlake FSP enables PchLockDownRtcMemoryLock by default, but we need this memory to be writable. We normally over-ride this in the SoC chip init code, so we'll do the same on cannonlake. BUG=b:71722386 BRANCH=none TEST=Filled /dev/nvram with 0xff and 0x00 bytes to verify we can flip all the bits. Change-Id: I7cdd4abc2b3795d7dd82236fbe3c112428ee882b Signed-off-by: Caveh Jalali Reviewed-on: https://review.coreboot.org/25069 Tested-by: build bot (Jenkins) Reviewed-by: Vincent Palatin --- src/soc/intel/cannonlake/chip.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'src/soc/intel') diff --git a/src/soc/intel/cannonlake/chip.c b/src/soc/intel/cannonlake/chip.c index 2187f906cf..ca2f9a35ec 100644 --- a/src/soc/intel/cannonlake/chip.c +++ b/src/soc/intel/cannonlake/chip.c @@ -200,6 +200,9 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) mainboard_silicon_init_params(params); + /* Unlock upper 8 bytes of RTC RAM */ + params->PchLockDownRtcMemoryLock = 0; + /* SATA */ params->SataEnable = config->SataEnable; params->SataMode = config->SataMode; -- cgit v1.2.3