From 1d85700503afdb8516ee945e9e294d4a6aa1c759 Mon Sep 17 00:00:00 2001 From: Alexandru Gagniuc Date: Wed, 9 Sep 2015 22:38:06 -0700 Subject: cpu: microcode: Use microcode stored in binary format Using a copiler to compile something that's already a binary is pretty stupid. Now that Stefan converted most microcode in blobs to a plain binary, use the binary version. Change-Id: Iecf1f0cdf7bbeb7a61f46a0cd984ba341af787ce Signed-off-by: Alexandru Gagniuc Reviewed-on: http://review.coreboot.org/11607 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/soc/intel/baytrail/Makefile.inc | 3 +- src/soc/intel/baytrail/microcode/Makefile.inc | 1 - src/soc/intel/baytrail/microcode/microcode_blob.c | 3 -- src/soc/intel/braswell/Makefile.inc | 3 +- src/soc/intel/braswell/microcode/Makefile.inc | 2 -- src/soc/intel/braswell/microcode/microcode_blob.c | 22 ------------- src/soc/intel/broadwell/Makefile.inc | 3 +- src/soc/intel/broadwell/microcode/Makefile.inc | 1 - src/soc/intel/broadwell/microcode/microcode_blob.c | 22 ------------- src/soc/intel/fsp_baytrail/Makefile.inc | 3 +- src/soc/intel/fsp_baytrail/microcode/Makefile.inc | 26 --------------- .../intel/fsp_baytrail/microcode/microcode_blob.c | 38 ---------------------- .../intel/fsp_baytrail/microcode/microcode_size.h | 6 ---- src/soc/intel/skylake/Makefile.inc | 3 +- src/soc/intel/skylake/microcode/Makefile.inc | 2 -- src/soc/intel/skylake/microcode/microcode_blob.c | 24 -------------- 16 files changed, 10 insertions(+), 152 deletions(-) delete mode 100644 src/soc/intel/baytrail/microcode/Makefile.inc delete mode 100644 src/soc/intel/baytrail/microcode/microcode_blob.c delete mode 100644 src/soc/intel/braswell/microcode/Makefile.inc delete mode 100644 src/soc/intel/braswell/microcode/microcode_blob.c delete mode 100644 src/soc/intel/broadwell/microcode/Makefile.inc delete mode 100644 src/soc/intel/broadwell/microcode/microcode_blob.c delete mode 100644 src/soc/intel/fsp_baytrail/microcode/Makefile.inc delete mode 100644 src/soc/intel/fsp_baytrail/microcode/microcode_blob.c delete mode 100644 src/soc/intel/fsp_baytrail/microcode/microcode_size.h delete mode 100644 src/soc/intel/skylake/microcode/Makefile.inc delete mode 100644 src/soc/intel/skylake/microcode/microcode_blob.c (limited to 'src/soc/intel') diff --git a/src/soc/intel/baytrail/Makefile.inc b/src/soc/intel/baytrail/Makefile.inc index 085a45e433..edc77af094 100644 --- a/src/soc/intel/baytrail/Makefile.inc +++ b/src/soc/intel/baytrail/Makefile.inc @@ -1,6 +1,5 @@ ifeq ($(CONFIG_SOC_INTEL_BAYTRAIL),y) -subdirs-y += microcode subdirs-y += romstage subdirs-y += ../../../cpu/x86/lapic subdirs-y += ../../../cpu/x86/mtrr @@ -53,6 +52,8 @@ ramstage-y += hda.c # Remove as ramstage gets fleshed out ramstage-y += placeholders.c +cpu_microcode_bins += 3rdparty/blobs/soc/intel/baytrail/microcode.bin + CPPFLAGS_common += -Isrc/soc/intel/baytrail/include # If an MRC file is an ELF file determine the entry address and first loadable diff --git a/src/soc/intel/baytrail/microcode/Makefile.inc b/src/soc/intel/baytrail/microcode/Makefile.inc deleted file mode 100644 index 09bd454ce0..0000000000 --- a/src/soc/intel/baytrail/microcode/Makefile.inc +++ /dev/null @@ -1 +0,0 @@ -cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c diff --git a/src/soc/intel/baytrail/microcode/microcode_blob.c b/src/soc/intel/baytrail/microcode/microcode_blob.c deleted file mode 100644 index a69990f0b9..0000000000 --- a/src/soc/intel/baytrail/microcode/microcode_blob.c +++ /dev/null @@ -1,3 +0,0 @@ -unsigned microcode[] = { -#include "../../../../../3rdparty/blobs/soc/intel/baytrail/microcode_blob.h" -}; diff --git a/src/soc/intel/braswell/Makefile.inc b/src/soc/intel/braswell/Makefile.inc index e5ac640610..426f3596b0 100644 --- a/src/soc/intel/braswell/Makefile.inc +++ b/src/soc/intel/braswell/Makefile.inc @@ -1,6 +1,5 @@ ifeq ($(CONFIG_SOC_INTEL_BRASWELL),y) -subdirs-y += microcode subdirs-y += romstage subdirs-y += ../../../cpu/x86/lapic subdirs-y += ../../../cpu/x86/mtrr @@ -51,6 +50,8 @@ smm-y += smihandler.c smm-y += spi.c smm-y += tsc_freq.c +# cpu_microcode_bins += ??? + CPPFLAGS_common += -I$(src)/soc/intel/braswell/ CPPFLAGS_common += -I$(src)/soc/intel/braswell/include diff --git a/src/soc/intel/braswell/microcode/Makefile.inc b/src/soc/intel/braswell/microcode/Makefile.inc deleted file mode 100644 index 3497328c3a..0000000000 --- a/src/soc/intel/braswell/microcode/Makefile.inc +++ /dev/null @@ -1,2 +0,0 @@ -# Add CPU uCode source to list of files to build. -cpu_microcode-y += microcode_blob.c diff --git a/src/soc/intel/braswell/microcode/microcode_blob.c b/src/soc/intel/braswell/microcode/microcode_blob.c deleted file mode 100644 index e0aeaffd61..0000000000 --- a/src/soc/intel/braswell/microcode/microcode_blob.c +++ /dev/null @@ -1,22 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc. - */ - -unsigned microcode[] = { -#include -}; diff --git a/src/soc/intel/broadwell/Makefile.inc b/src/soc/intel/broadwell/Makefile.inc index fdd064de2e..a9004ac8dd 100644 --- a/src/soc/intel/broadwell/Makefile.inc +++ b/src/soc/intel/broadwell/Makefile.inc @@ -1,6 +1,5 @@ ifeq ($(CONFIG_SOC_INTEL_BROADWELL),y) -subdirs-y += microcode subdirs-y += romstage subdirs-y += ../../../cpu/x86/lapic subdirs-y += ../../../cpu/x86/mtrr @@ -73,6 +72,8 @@ romstage-y += usbdebug.c smm-y += usbdebug.c endif +cpu_microcode_bins += 3rdparty/blobs/soc/intel/broadwell/microcode.bin + CPPFLAGS_common += -Isrc/soc/intel/broadwell/include # If an MRC file is an ELF file determine the entry address and first loadable diff --git a/src/soc/intel/broadwell/microcode/Makefile.inc b/src/soc/intel/broadwell/microcode/Makefile.inc deleted file mode 100644 index bf9e345dbd..0000000000 --- a/src/soc/intel/broadwell/microcode/Makefile.inc +++ /dev/null @@ -1 +0,0 @@ -cpu_microcode-y += microcode_blob.c diff --git a/src/soc/intel/broadwell/microcode/microcode_blob.c b/src/soc/intel/broadwell/microcode/microcode_blob.c deleted file mode 100644 index 412fedcba1..0000000000 --- a/src/soc/intel/broadwell/microcode/microcode_blob.c +++ /dev/null @@ -1,22 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc. - */ - -unsigned microcode[] = { -#include "../../../../../3rdparty/blobs/soc/intel/broadwell/microcode_blob.h" -}; diff --git a/src/soc/intel/fsp_baytrail/Makefile.inc b/src/soc/intel/fsp_baytrail/Makefile.inc index 39a253f692..7370830fc6 100644 --- a/src/soc/intel/fsp_baytrail/Makefile.inc +++ b/src/soc/intel/fsp_baytrail/Makefile.inc @@ -20,7 +20,6 @@ ifeq ($(CONFIG_SOC_INTEL_FSP_BAYTRAIL),y) -subdirs-y += microcode subdirs-y += romstage subdirs-y += ../../../cpu/x86/lapic subdirs-y += ../../../cpu/x86/mtrr @@ -59,6 +58,8 @@ ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smm.c ramstage-y += placeholders.c ramstage-y += i2c.c +cpu_microcode_bins += 3rdparty/blobs/soc/intel/baytrail/microcode.bin + CPPFLAGS_common += -I$(src)/soc/intel/fsp_baytrail/ CPPFLAGS_common += -I$(src)/soc/intel/fsp_baytrail/fsp diff --git a/src/soc/intel/fsp_baytrail/microcode/Makefile.inc b/src/soc/intel/fsp_baytrail/microcode/Makefile.inc deleted file mode 100644 index 506291d301..0000000000 --- a/src/soc/intel/fsp_baytrail/microcode/Makefile.inc +++ /dev/null @@ -1,26 +0,0 @@ -# -# This file is part of the coreboot project. -# -# Copyright (C) 2014 Sage Electronic Engineering, LLC. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc. -# -cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c -CPPFLAGS_romstage += -I$(src)/soc/intel/fsp_baytrail/microcode - -ifneq ($(CONFIG_MICROCODE_INCLUDE_PATH),) -ifneq ($(wildcard $(shell readlink -f "$(top)/$(CONFIG_MICROCODE_INCLUDE_PATH)")),) -CPPFLAGS_common += -I$(CONFIG_MICROCODE_INCLUDE_PATH) -endif -endif diff --git a/src/soc/intel/fsp_baytrail/microcode/microcode_blob.c b/src/soc/intel/fsp_baytrail/microcode/microcode_blob.c deleted file mode 100644 index 822c91baf5..0000000000 --- a/src/soc/intel/fsp_baytrail/microcode/microcode_blob.c +++ /dev/null @@ -1,38 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc. - */ - -unsigned microcode[] = { - - /* - * The problem is that these microcode files are not in the tree. They come - * with FSP, so let the user deal with the include paths when HAVE_FSP_BIN - * is enabled. - */ -#if IS_ENABLED(CONFIG_HAVE_FSP_BIN) -#if !IS_ENABLED(CONFIG_SOC_INTEL_FSP_BAYTRAIL_MD) - /* Region size is 0x30000 - update in microcode_size.h if it gets larger. */ - #include "M0230672228.h" // M0230672: Bay Trail "Super SKU" B0/B1 - #include "M0130673322.h" // M0130673: Bay Trail I B2 / B3 - #include "M0130679901.h" // M0130679: Bay Trail I D0 -#else - /* Region size is 0x10000 - update in microcode_size.h if it gets larger. */ - #include "M0C30678829.h" // M0C30678: Bay Trail M D Stepping -#endif /* CONFIG_SOC_INTEL_FSP_BAYTRAIL_MD */ -#endif /* CONFIG_HAVE_FSP_BIN */ -}; diff --git a/src/soc/intel/fsp_baytrail/microcode/microcode_size.h b/src/soc/intel/fsp_baytrail/microcode/microcode_size.h deleted file mode 100644 index 2af22016cb..0000000000 --- a/src/soc/intel/fsp_baytrail/microcode/microcode_size.h +++ /dev/null @@ -1,6 +0,0 @@ -/* Maximum size of the area that the FSP will search for the correct microcode */ -#if !IS_ENABLED(CONFIG_SOC_INTEL_FSP_BAYTRAIL_MD) - #define MICROCODE_REGION_LENGTH 0x30000 -#else - #define MICROCODE_REGION_LENGTH 0x10000 -#endif diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc index d6bc839128..b80767bff3 100644 --- a/src/soc/intel/skylake/Makefile.inc +++ b/src/soc/intel/skylake/Makefile.inc @@ -1,6 +1,5 @@ ifeq ($(CONFIG_SOC_INTEL_SKYLAKE),y) -subdirs-y += microcode subdirs-y += romstage subdirs-y += ../../../cpu/intel/microcode subdirs-y += ../../../cpu/intel/turbo @@ -61,6 +60,8 @@ smm-$(CONFIG_SPI_FLASH_SMM) += flash_controller.c smm-y += tsc_freq.c smm-$(CONFIG_UART_DEBUG) += uart_debug.c +# cpu_microcode_bins += ??? + CPPFLAGS_common += -I$(src)/soc/intel/skylake CPPFLAGS_common += -I$(src)/soc/intel/skylake/include diff --git a/src/soc/intel/skylake/microcode/Makefile.inc b/src/soc/intel/skylake/microcode/Makefile.inc deleted file mode 100644 index ba308f633a..0000000000 --- a/src/soc/intel/skylake/microcode/Makefile.inc +++ /dev/null @@ -1,2 +0,0 @@ -# Add CPU uCode source to list of files to build. -cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c diff --git a/src/soc/intel/skylake/microcode/microcode_blob.c b/src/soc/intel/skylake/microcode/microcode_blob.c deleted file mode 100644 index 48c1aa2835..0000000000 --- a/src/soc/intel/skylake/microcode/microcode_blob.c +++ /dev/null @@ -1,24 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc. - */ - -unsigned int microcode[] = { -#include -}; - -- cgit v1.2.3