From 1bfd56cb2509c239ed683667e61789a4ba5d3079 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Mon, 24 Feb 2020 15:14:22 +0530 Subject: soc/intel/tigerlake: Integrate Legacy 8254 timer support This patch overrides required FSP-S UPDs to enable 8254 timer support for TGL if CONFIG_USE_LEGACY_8254_TIMER is selected. TEST=Required to boot TianoCore payload. Change-Id: Iaeff5c4b92691ed6ba7b71541ed4f947d5d299a8 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/39098 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak Reviewed-by: Wonkyu Kim --- src/soc/intel/tigerlake/fsp_params_tgl.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'src/soc/intel') diff --git a/src/soc/intel/tigerlake/fsp_params_tgl.c b/src/soc/intel/tigerlake/fsp_params_tgl.c index 305748e8f3..d22cde021c 100644 --- a/src/soc/intel/tigerlake/fsp_params_tgl.c +++ b/src/soc/intel/tigerlake/fsp_params_tgl.c @@ -135,6 +135,10 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) sizeof(params->SataPortsDevSlp)); } + /* Legacy 8254 timer support */ + params->Enable8254ClockGating = !CONFIG_USE_LEGACY_8254_TIMER; + params->Enable8254ClockGatingOnS3 = !CONFIG_USE_LEGACY_8254_TIMER; + mainboard_silicon_init_params(params); } -- cgit v1.2.3