From 17a3da8b9946dde434c7f1ab8cf14cbb1597373b Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Thu, 24 Nov 2022 21:51:42 +0530 Subject: soc/intel/cmn/cse: API to perform essential CSE operations post EOP This patch creates an API that can perform essential CSE operation after sending the late EOP command to the CSE and prior booting to OS. Lists of operation are - Perform global reset lock - Put HECI1 to D0i3 and disable the HECI1 if the user selects - Set D0I3 for all HECI devices. BUG=b:260041679 TEST=Able to boot Google/Rex after sending CSE EOP late. Signed-off-by: Subrata Banik Change-Id: I10131ea9b553a62f0d632783c4dbad96d35d6563 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69977 Reviewed-by: Kapil Porwal Reviewed-by: Lean Sheng Tan Tested-by: build bot (Jenkins) --- src/soc/intel/common/block/cse/cse.c | 16 ++++++++++++++++ src/soc/intel/common/block/include/intelblocks/cse.h | 6 ++++++ 2 files changed, 22 insertions(+) (limited to 'src/soc/intel') diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index 9b8db54efd..8f32c7ce61 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -1255,6 +1255,22 @@ static void cse_final_end_of_firmware(void) heci_set_to_d0i3(); } +/* + * This function to perform essential post EOP cse related operations + * upon SoC selecting `SOC_INTEL_CSE_SEND_EOP_LATE` config + */ +void cse_late_finalize(void) +{ + if (!CONFIG(SOC_INTEL_CSE_SEND_EOP_LATE)) + return; + + if (!CONFIG(USE_FSP_NOTIFY_PHASE_READY_TO_BOOT)) + cse_final_ready_to_boot(); + + if (!CONFIG(USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE)) + cse_final_end_of_firmware(); +} + /* * `cse_final` function is native implementation of equivalent events performed by * each FSP NotifyPhase() API invocations. diff --git a/src/soc/intel/common/block/include/intelblocks/cse.h b/src/soc/intel/common/block/include/intelblocks/cse.h index cceee4f8ac..bccdc4ead4 100644 --- a/src/soc/intel/common/block/include/intelblocks/cse.h +++ b/src/soc/intel/common/block/include/intelblocks/cse.h @@ -541,6 +541,12 @@ void cse_control_global_reset_lock(void); /* Send End of Post (EOP) command to CSE device */ void cse_send_end_of_post(void); +/* + * This function to perform essential post EOP cse related operations + * upon SoC selecting `SOC_INTEL_CSE_SEND_EOP_LATE` config + */ +void cse_late_finalize(void); + /* * SoC override API to make heci1 disable using PCR. * -- cgit v1.2.3