From 156bc6f47a7c4536649f79ee037c7eed063d1805 Mon Sep 17 00:00:00 2001 From: Shelley Chen Date: Tue, 29 Sep 2020 10:05:00 -0700 Subject: soc/intel/braswell: Increase dcache size Increase the DRAM cache size for Braswell to address the compilation error Cache as RAM area too full when moving the mrc_cache writeback to romstage. We need to increase this first before landing the CL moving mrc_cache writeback to romstage. BUG=b:150502246 BRANCH=None TEST=Able to successfully compile braswell boards Change-Id: I1538d504ddad8654c79a789e58ffe6b11b5d544c Signed-off-by: Shelley Chen Reviewed-on: https://review.coreboot.org/c/coreboot/+/45827 Reviewed-by: Furquan Shaikh Tested-by: build bot (Jenkins) --- src/soc/intel/braswell/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/soc/intel') diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig index ae4fc21e37..4eb810ea93 100644 --- a/src/soc/intel/braswell/Kconfig +++ b/src/soc/intel/braswell/Kconfig @@ -93,7 +93,7 @@ config DCACHE_RAM_BASE config DCACHE_RAM_SIZE hex - default 0x4000 + default 0x8000 help The size of the cache-as-ram region required during bootblock and/or romstage. Note DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZE -- cgit v1.2.3