From 11fdb17564bd4d3e3539c9855be88dd7e5fd8061 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Fri, 30 Oct 2020 14:18:40 +0100 Subject: soc/intel/broadwell/pch/sata.c: Don't enable Bus Master Bus Master is not required and reference code does not set it. Change-Id: I2f70486f96cf3dcaba74283293b93b9747cd0300 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/47026 Tested-by: build bot (Jenkins) Reviewed-by: Felix Singer --- src/soc/intel/broadwell/pch/sata.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) (limited to 'src/soc/intel') diff --git a/src/soc/intel/broadwell/pch/sata.c b/src/soc/intel/broadwell/pch/sata.c index b496e53e3d..82760aba86 100644 --- a/src/soc/intel/broadwell/pch/sata.c +++ b/src/soc/intel/broadwell/pch/sata.c @@ -35,9 +35,8 @@ static void sata_init(struct device *dev) printk(BIOS_DEBUG, "SATA: Initializing controller in AHCI mode.\n"); - /* Enable BARs */ - pci_write_config16(dev, PCI_COMMAND, - PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO); + /* Enable memory space decoding for ABAR */ + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_IO); /* Set Interrupt Line */ /* Interrupt Pin is set by D31IP.PIP */ -- cgit v1.2.3