From 0d0f43f9d36f3a942322486b486b98f7ae5cd70d Mon Sep 17 00:00:00 2001
From: Shaunak Saha <shaunak.saha@intel.com>
Date: Wed, 2 Sep 2020 15:37:00 -0700
Subject: soc/intel/tigerlake: Add Acoustic features

Expose the following FSP UPD interface into coreboot:
- AcousticNoiseMitigation
- FastPkgCRampDisable
- SlowSlewRateFor

BUG=b:153015585
BRANCH=none
TEST= Measure the change in noise level by changing the UPD values.

Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Change-Id: I1924a3bac8beb16a9d841891696f9a3dea0d425f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45052
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
---
 src/soc/intel/tigerlake/chip.h       | 53 ++++++++++++++++++++++++++++++++++++
 src/soc/intel/tigerlake/fsp_params.c |  8 ++++++
 2 files changed, 61 insertions(+)

(limited to 'src/soc/intel')

diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h
index bcf71b1e62..fb6cda0919 100644
--- a/src/soc/intel/tigerlake/chip.h
+++ b/src/soc/intel/tigerlake/chip.h
@@ -68,6 +68,33 @@ enum lpm_state_mask {
 		     | LPM_S0i3_0 | LPM_S0i3_1 | LPM_S0i3_2 | LPM_S0i3_3 | LPM_S0i3_4,
 };
 
+/*
+ * VR domains. The domains are IA,GT,SA,VLCC and FIVR.
+ */
+enum vr_domains {
+	VR_DOMAIN_IA,
+	VR_DOMAIN_GT,
+	VR_DOMAIN_SA,
+	VR_DOMAIN_VLCC,
+	VR_DOMAIN_FIVR,
+	VR_DOMAIN_MAX
+};
+
+/*
+ * Slew Rate configuration for Deep Package C States for VR domain.
+ * They are fast time divided by 2.
+ * 0 - Fast/2
+ * 1 - Fast/4
+ * 2 - Fast/8
+ * 3 - Fast/16
+ */
+enum slew_rate {
+	SLEW_FAST_2,
+	SLEW_FAST_4,
+	SLEW_FAST_8,
+	SLEW_FAST_16
+};
+
 struct soc_intel_tigerlake_config {
 
 	/* Common struct containing soc config data required by common code */
@@ -143,6 +170,32 @@ struct soc_intel_tigerlake_config {
 	/* Wake Enable Bitmap for USB3 ports */
 	uint16_t usb3_wake_enable_bitmap;
 
+	/*
+	 * Acoustic Noise Mitigation
+	 * 0 - Disable
+	 * 1 - Enable noise mitigation
+	 */
+	uint8_t AcousticNoiseMitigation;
+
+	/*
+	 * Offset 0x054B - Disable Fast Slew Rate for Deep Package
+	 * C States for VR domains. Disable Fast Slew Rate for Deep
+	 * Package C States based on Acoustic Noise Mitigation feature
+	 * enabled. The domains are IA,GT,SA,VLCC and FIVR.
+	 * 0 - False
+	 * 1 - True
+	 */
+	uint8_t FastPkgCRampDisable[VR_DOMAIN_MAX];
+
+	/*
+	 * Offset 0x0550 - Slew Rate configuration for Deep Package
+	 * C States for VR domains. Slew Rate configuration for Deep
+	 * Package C States for VR domains based on Acoustic Noise
+	 * Mitigation feature enabled. The domains are IA,GT,SA,VLCC and FIVR.
+	 * Slew rates are defined as enum slew_rate.
+	 */
+	uint8_t SlowSlewRate[VR_DOMAIN_MAX];
+
 	/* SATA related */
 	uint8_t SataEnable;
 	uint8_t SataMode;
diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c
index 38f444bbd5..887241b5c2 100644
--- a/src/soc/intel/tigerlake/fsp_params.c
+++ b/src/soc/intel/tigerlake/fsp_params.c
@@ -256,6 +256,14 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
 		}
 	}
 
+	params->AcousticNoiseMitigation = config->AcousticNoiseMitigation;
+	memcpy(&params->SlowSlewRate, &config->SlowSlewRate,
+		ARRAY_SIZE(config->SlowSlewRate) * sizeof(config->SlowSlewRate[0]));
+
+	memcpy(&params->FastPkgCRampDisable, &config->FastPkgCRampDisable,
+		ARRAY_SIZE(config->FastPkgCRampDisable) *
+			sizeof(config->FastPkgCRampDisable[0]));
+
 	/* Enable TCPU for processor thermal control */
 	params->Device4Enable = config->Device4Enable;
 
-- 
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