From 0180e43f3d7ecc17091a80d3892ecb06e6707efc Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Fri, 18 Sep 2020 14:42:03 +0530 Subject: soc/intel/common: Keep common non-IP code block inside basecode MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Expand the scope of 'common/basecode' directory to keep common non-IP code block (like acpi, power limit). Signed-off-by: Subrata Banik Change-Id: I7a2778704016b501eb20382d4603295cec8375d5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45522 Reviewed-by: Furquan Shaikh Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) --- src/soc/intel/common/Kconfig.common | 4 ++-- src/soc/intel/common/basecode/Kconfig | 3 +-- 2 files changed, 3 insertions(+), 4 deletions(-) (limited to 'src/soc/intel') diff --git a/src/soc/intel/common/Kconfig.common b/src/soc/intel/common/Kconfig.common index 44c2392abc..eae8e85535 100644 --- a/src/soc/intel/common/Kconfig.common +++ b/src/soc/intel/common/Kconfig.common @@ -6,13 +6,13 @@ config SOC_INTEL_COMMON if SOC_INTEL_COMMON -comment "Intel SoC Common Code" +comment "Intel SoC Common Code for IP blocks" source "src/soc/intel/common/block/Kconfig" comment "Intel SoC Common PCH Code" source "src/soc/intel/common/pch/Kconfig" -comment "Intel SoC Common coreboot stages" +comment "Intel SoC Common coreboot stages and non-IP blocks" source "src/soc/intel/common/basecode/Kconfig" config SOC_INTEL_COMMON_RESET diff --git a/src/soc/intel/common/basecode/Kconfig b/src/soc/intel/common/basecode/Kconfig index 68aea15671..1c93244573 100644 --- a/src/soc/intel/common/basecode/Kconfig +++ b/src/soc/intel/common/basecode/Kconfig @@ -1,11 +1,10 @@ config SOC_INTEL_COMMON_BASECODE bool help - Common coreboot stages for Intel platform + Common coreboot stages and non-IP block for Intel platform if SOC_INTEL_COMMON_BASECODE -comment "Intel platform Common coreboot stage files" source "src/soc/intel/common/basecode/*/Kconfig" source "src/soc/intel/common/basecode/*/*/Kconfig" -- cgit v1.2.3