From ffc5a1ce301b2feae6f5ee7cc6480dce18db9b81 Mon Sep 17 00:00:00 2001 From: Jonathan Zhang Date: Mon, 23 Jan 2023 16:33:03 -0800 Subject: soc/intel/xeon_sp: Use simple device function for setting PMAX_LOCK Change to use simple device function for setting PMAX_LOCK because the Sapphire Rapids PCU device is not scanned during coreboot PCIe bus scan and would see "PCI: dev is NULL!" failure. Change-Id: I3156a6adf874b324b5f4ff5857c40002220e47ab Signed-off-by: Marc Jones Signed-off-by: Johnny Lin Reviewed-on: https://review.coreboot.org/c/coreboot/+/72400 Reviewed-by: Simon Chou Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Lean Sheng Tan --- src/soc/intel/xeon_sp/util.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'src/soc/intel/xeon_sp') diff --git a/src/soc/intel/xeon_sp/util.c b/src/soc/intel/xeon_sp/util.c index c4a10f9a9c..7524e52900 100644 --- a/src/soc/intel/xeon_sp/util.c +++ b/src/soc/intel/xeon_sp/util.c @@ -320,7 +320,9 @@ static void set_bios_init_completion_for_package(uint32_t socket) die("BIOS RESET CPL3 timed out.\n"); /* Set PMAX_LOCK - must be set before RESET CPL4 */ - pci_or_config32(PCU_DEV_CR0(bus), PCU_CR0_PMAX, PMAX_LOCK); + data = pci_s_read_config32(PCI_DEV(bus, PCU_DEV, PCU_CR0_FUN), PCU_CR0_PMAX); + data |= PMAX_LOCK; + pci_s_write_config32(PCI_DEV(bus, PCU_DEV, PCU_CR0_FUN), PCU_CR0_PMAX, data); /* update RST_CPL4, PCODE_INIT_DONE4 */ timedout = set_bios_reset_cpl_for_package(socket, RST_CPL4_MASK, -- cgit v1.2.3