From e07ea4cd38c5c232515a8755d2b4fbff6f12b949 Mon Sep 17 00:00:00 2001 From: Jingle Hsu Date: Wed, 1 Jul 2020 18:26:49 +0800 Subject: soc/intel/xeon_sp: Add RTC failure checking Add a weak function mainboard_rtc_failed() for mainboard customization. Check RTC_PWR_STS bit for RTC battery removal or CMOS clear jumper triggered event. Signed-off-by: Jingle Hsu Change-Id: Ic6da84277e71a5c51dfa4d97d5d0c0184478e8f0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43004 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/soc/intel/xeon_sp/Makefile.inc | 2 +- src/soc/intel/xeon_sp/include/soc/pmc.h | 2 +- src/soc/intel/xeon_sp/include/soc/romstage.h | 1 + src/soc/intel/xeon_sp/pmutil.c | 23 +++++++++++++++++++++++ src/soc/intel/xeon_sp/romstage.c | 7 +++++++ 5 files changed, 33 insertions(+), 2 deletions(-) create mode 100644 src/soc/intel/xeon_sp/pmutil.c (limited to 'src/soc/intel/xeon_sp') diff --git a/src/soc/intel/xeon_sp/Makefile.inc b/src/soc/intel/xeon_sp/Makefile.inc index 9589e5a88b..94c1764659 100644 --- a/src/soc/intel/xeon_sp/Makefile.inc +++ b/src/soc/intel/xeon_sp/Makefile.inc @@ -6,7 +6,7 @@ subdirs-$(CONFIG_SOC_INTEL_SKYLAKE_SP) += skx subdirs-$(CONFIG_SOC_INTEL_COOPERLAKE_SP) += cpx bootblock-y += bootblock.c spi.c lpc.c gpio.c pch.c -romstage-y += romstage.c reset.c util.c spi.c gpio.c +romstage-y += romstage.c reset.c util.c spi.c gpio.c pmutil.c ramstage-y += uncore.c reset.c util.c lpc.c spi.c gpio.c postcar-y += spi.c diff --git a/src/soc/intel/xeon_sp/include/soc/pmc.h b/src/soc/intel/xeon_sp/include/soc/pmc.h index d3bad1b715..49e58d366a 100644 --- a/src/soc/intel/xeon_sp/include/soc/pmc.h +++ b/src/soc/intel/xeon_sp/include/soc/pmc.h @@ -25,6 +25,6 @@ #define GEN_PMCON_B 0xa4 #define SLP_STR_POL_LOCK (1 << 18) #define ACPI_BASE_LOCK (1 << 17) - +#define RTC_BATTERY_DEAD (1 << 2) #endif diff --git a/src/soc/intel/xeon_sp/include/soc/romstage.h b/src/soc/intel/xeon_sp/include/soc/romstage.h index 42425e29d0..8bd5709fe0 100644 --- a/src/soc/intel/xeon_sp/include/soc/romstage.h +++ b/src/soc/intel/xeon_sp/include/soc/romstage.h @@ -8,5 +8,6 @@ /* These functions are weak and can be overridden by a mainboard functions. */ void mainboard_memory_init_params(FSPM_UPD * mupd); +void mainboard_rtc_failed(void); #endif /* _SOC_ROMSTAGE_H_ */ diff --git a/src/soc/intel/xeon_sp/pmutil.c b/src/soc/intel/xeon_sp/pmutil.c new file mode 100644 index 0000000000..9ab63a4f0b --- /dev/null +++ b/src/soc/intel/xeon_sp/pmutil.c @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * Helper functions for dealing with power management registers + * and the differences between PCH variants. + */ + +#include +#include +#include +#include +#include + +int soc_get_rtc_failed(void) +{ + uint32_t pmcon_b = pci_s_read_config32(PCH_DEV_PMC, GEN_PMCON_B); + int rtc_fail = !!(pmcon_b & RTC_BATTERY_DEAD); + + if (rtc_fail) + printk(BIOS_ERR, "%s: RTC battery dead or removed\n", __func__); + + return rtc_fail; +} diff --git a/src/soc/intel/xeon_sp/romstage.c b/src/soc/intel/xeon_sp/romstage.c index 3db9ca9f9e..a4853c064e 100644 --- a/src/soc/intel/xeon_sp/romstage.c +++ b/src/soc/intel/xeon_sp/romstage.c @@ -18,6 +18,8 @@ asmlinkage void car_stage_entry(void) console_init(); rtc_init(); + if (soc_get_rtc_failed()) + mainboard_rtc_failed(); fsp_memory_init(false); printk(BIOS_DEBUG, "coreboot fsp_memory_init finished...\n"); @@ -47,3 +49,8 @@ __weak void mainboard_memory_init_params(FSPM_UPD *mupd) { printk(BIOS_SPEW, "WARNING: using default FSP-M parameters!\n"); } + +__weak void mainboard_rtc_failed(void) +{ + +} -- cgit v1.2.3