From d4f2d14d52cba27f25a53979548ea9bdaf71c23e Mon Sep 17 00:00:00 2001 From: Dinesh Gehlot Date: Fri, 16 Dec 2022 09:21:18 +0000 Subject: soc/intel: Move max speed API to common This patch moves API "smbios_cpu_get_max_speed_mhz()" to common code from board specific. This API was made generic in 'commit d34364bdea12 ("soc/intel/alderlake: Utilize `CPU_BCLK_MHZ` over dedicated macro")' BUG=NONE TEST=Boot and verified that SMBIOS max speed value is correct on brya and rex. (brya) dmidecode -t : "Max Speed: 4400 MHz" (rex) dmidecode -t : "Max Speed: 3400 MHz" Signed-off-by: Dinesh Gehlot Change-Id: I87040ab23319097287e191d7fc9579f16d716e62 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70879 Reviewed-by: Johnny Lin Reviewed-by: Eric Lai Reviewed-by: Subrata Banik Reviewed-by: Kapil Porwal Tested-by: build bot (Jenkins) --- src/soc/intel/xeon_sp/cpx/Makefile.inc | 2 +- src/soc/intel/xeon_sp/cpx/ramstage.c | 8 -------- 2 files changed, 1 insertion(+), 9 deletions(-) delete mode 100644 src/soc/intel/xeon_sp/cpx/ramstage.c (limited to 'src/soc/intel/xeon_sp') diff --git a/src/soc/intel/xeon_sp/cpx/Makefile.inc b/src/soc/intel/xeon_sp/cpx/Makefile.inc index d2a1583fe8..593c339f45 100644 --- a/src/soc/intel/xeon_sp/cpx/Makefile.inc +++ b/src/soc/intel/xeon_sp/cpx/Makefile.inc @@ -9,7 +9,7 @@ romstage-y += romstage.c ddr.c romstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c romstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c -ramstage-y += chip.c cpu.c soc_util.c ramstage.c soc_acpi.c +ramstage-y += chip.c cpu.c soc_util.c soc_acpi.c ramstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c ramstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c diff --git a/src/soc/intel/xeon_sp/cpx/ramstage.c b/src/soc/intel/xeon_sp/cpx/ramstage.c deleted file mode 100644 index cd1b038b52..0000000000 --- a/src/soc/intel/xeon_sp/cpx/ramstage.c +++ /dev/null @@ -1,8 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include - -unsigned int smbios_cpu_get_max_speed_mhz(void) -{ - return 3900; -} -- cgit v1.2.3