From 8670e829a8f2f6e56c2405333a171c2bc7cd017b Mon Sep 17 00:00:00 2001 From: Andrey Petrov Date: Mon, 30 Mar 2020 12:25:06 -0700 Subject: soc/intel/xeon_sp/cpx: Add multi-core init Add minimal MP init. No SMM, no turbo, not c/p states. TEST=boot linux kernel, observe CPUs are online, schedule tasks and perform useful work. Tested on Cedar Island CRB with only 1 socket populated Change-Id: I0af374ab3956009e9208917d911d29eb21db6069 Signed-off-by: Andrey Petrov Reviewed-on: https://review.coreboot.org/c/coreboot/+/40035 Tested-by: build bot (Jenkins) Reviewed-by: Maxim Polyakov --- src/soc/intel/xeon_sp/cpx/Makefile.inc | 3 +- src/soc/intel/xeon_sp/cpx/chip.c | 8 +-- src/soc/intel/xeon_sp/cpx/cpu.c | 86 +++++++++++++++++++++++++++++ src/soc/intel/xeon_sp/cpx/include/soc/cpu.h | 11 +++- 4 files changed, 100 insertions(+), 8 deletions(-) create mode 100644 src/soc/intel/xeon_sp/cpx/cpu.c (limited to 'src/soc/intel/xeon_sp') diff --git a/src/soc/intel/xeon_sp/cpx/Makefile.inc b/src/soc/intel/xeon_sp/cpx/Makefile.inc index b909a454bd..e00ae40637 100644 --- a/src/soc/intel/xeon_sp/cpx/Makefile.inc +++ b/src/soc/intel/xeon_sp/cpx/Makefile.inc @@ -8,9 +8,10 @@ ifeq ($(CONFIG_SOC_INTEL_COOPERLAKE_SP),y) subdirs-y += ../../../../cpu/x86/lapic subdirs-y += ../../../../cpu/x86/mtrr subdirs-y += ../../../../cpu/x86/tsc +subdirs-y += ../../../../cpu/intel/microcode romstage-y += romstage.c -ramstage-y += chip.c acpi.c +ramstage-y += chip.c acpi.c cpu.c CPPFLAGS_common += -I$(src)/soc/intel/xeon_sp/cpx/include -I$(src)/soc/intel/xeon_sp/cpx diff --git a/src/soc/intel/xeon_sp/cpx/chip.c b/src/soc/intel/xeon_sp/cpx/chip.c index dbbf3b31a5..e4063dc99d 100644 --- a/src/soc/intel/xeon_sp/cpx/chip.c +++ b/src/soc/intel/xeon_sp/cpx/chip.c @@ -7,6 +7,7 @@ #include #include #include +#include #include #include @@ -29,16 +30,11 @@ static struct device_operations pci_domain_ops = { .scan_bus = &pci_domain_scan_bus, }; -static void init_cpus(struct device *dev) -{ - /* not implemented yet */ -} - static struct device_operations cpu_bus_ops = { .read_resources = DEVICE_NOOP, .set_resources = DEVICE_NOOP, .enable_resources = DEVICE_NOOP, - .init = init_cpus, + .init = cpx_init_cpus, .scan_bus = NULL, }; diff --git a/src/soc/intel/xeon_sp/cpx/cpu.c b/src/soc/intel/xeon_sp/cpx/cpu.c new file mode 100644 index 0000000000..8824686674 --- /dev/null +++ b/src/soc/intel/xeon_sp/cpx/cpu.c @@ -0,0 +1,86 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static const void *microcode_patch; + +void get_microcode_info(const void **microcode, int *parallel) +{ + *microcode = intel_mp_current_microcode(); + *parallel = 1; +} + +const void *intel_mp_current_microcode(void) +{ + return microcode_patch; +} + +static void each_cpu_init(struct device *cpu) +{ + printk(BIOS_INFO, "%s dev: %s, cpu: %d, apic_id: 0x%x\n", + __func__, dev_path(cpu), cpu_index(), cpu->path.apic.apic_id); + + setup_lapic(); +} + +static struct device_operations cpu_dev_ops = { + .init = each_cpu_init, +}; + +static const struct cpu_device_id cpu_table[] = { + {X86_VENDOR_INTEL, CPUID_COOPERLAKE_SP_A0}, + {0, 0}, +}; + +static const struct cpu_driver driver __cpu_driver = { + .ops = &cpu_dev_ops, + .id_table = cpu_table, +}; + +/* + * Do essential initialization tasks before APs can be fired up + */ +static void pre_mp_init(void) +{ + x86_setup_mtrrs_with_detect(); + x86_mtrr_check(); +} + +static int get_thread_count(void) +{ + unsigned int num_phys = 0, num_virts = 0; + + cpu_read_topology(&num_phys, &num_virts); + printk(BIOS_SPEW, "Detected %u cores and %u threads\n", num_phys, num_virts); + return num_virts; +} + +static const struct mp_ops mp_ops = { + .pre_mp_init = pre_mp_init, + .get_cpu_count = get_thread_count, + .get_microcode_info = get_microcode_info +}; + +void cpx_init_cpus(struct device *dev) +{ + microcode_patch = intel_microcode_find(); + + if (!microcode_patch) + printk(BIOS_ERR, "microcode not found in CBFS!\n"); + + intel_microcode_load_unlocked(microcode_patch); + + if (mp_init_with_smm(dev->link_list, &mp_ops) < 0) + printk(BIOS_ERR, "MP initialization failure.\n"); +} diff --git a/src/soc/intel/xeon_sp/cpx/include/soc/cpu.h b/src/soc/intel/xeon_sp/cpx/include/soc/cpu.h index f33df89a60..563270d135 100644 --- a/src/soc/intel/xeon_sp/cpx/include/soc/cpu.h +++ b/src/soc/intel/xeon_sp/cpx/include/soc/cpu.h @@ -1,4 +1,13 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -/* nothing here yet */ +#ifndef _SOC_CPU_H +#define _SOC_CPU_H + +#include + +#define CPUID_COOPERLAKE_SP_A0 0x05065a + +void cpx_init_cpus(struct device *dev); + +#endif -- cgit v1.2.3