From 8331833c89b3413ed4c3aef4a4cab762620911d0 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Mon, 18 Jan 2021 20:00:35 +0100 Subject: soc/intel/xeon_sp/cpx: Fix loading MCU on APs Commit 393992f (cpu/mp_init: Fix microcode lock) fixed the semantics of parallel loading microcode updates. So now '*parallel = 1' really means loading MCU in parallel, which seems to fail inconsistently on around 10% of the APs. Change-Id: I755dd302abbb58537d840852e8e290bea282a674 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/49671 Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/soc/intel/xeon_sp/cpx/cpu.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) (limited to 'src/soc/intel/xeon_sp') diff --git a/src/soc/intel/xeon_sp/cpx/cpu.c b/src/soc/intel/xeon_sp/cpx/cpu.c index 2f4ab0663e..4dea1a40a6 100644 --- a/src/soc/intel/xeon_sp/cpx/cpu.c +++ b/src/soc/intel/xeon_sp/cpx/cpu.c @@ -51,10 +51,15 @@ static void xeon_configure_mca(void) mca_configure(); } +/* + * On server platforms the FIT mechanism only updates the microcode on + * the BSP. Loading MCU on AP in parallel seems to fail in 10% of the cases + * so do it serialized. + */ void get_microcode_info(const void **microcode, int *parallel) { *microcode = intel_mp_current_microcode(); - *parallel = 1; + *parallel = 0; } const void *intel_mp_current_microcode(void) -- cgit v1.2.3