From 6c708d8a467e7027cd841896b8f5cbc8555fb254 Mon Sep 17 00:00:00 2001 From: Shuo Liu Date: Mon, 29 Apr 2024 18:16:30 +0800 Subject: soc/intel/xeon_sp: Add domain resource window creation utils It might be benefical to have utils for domain resource window creation so that the correct IORESOURCE flags used could be guaranteed. TEST=Build and boot on intel/archercity CRB TEST=Build on intel/avenuecity CRB Change-Id: I1e90512a48ab002a1c1d5031585ddadaac63673e Signed-off-by: Shuo Liu Reviewed-on: https://review.coreboot.org/c/coreboot/+/82103 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- src/soc/intel/xeon_sp/chip_gen1.c | 64 ++++++++++++--------------------------- src/soc/intel/xeon_sp/chip_gen6.c | 30 ++++++------------ src/soc/intel/xeon_sp/spr/ioat.c | 18 +++-------- 3 files changed, 33 insertions(+), 79 deletions(-) (limited to 'src/soc/intel/xeon_sp') diff --git a/src/soc/intel/xeon_sp/chip_gen1.c b/src/soc/intel/xeon_sp/chip_gen1.c index b17b77347e..117de9ca00 100644 --- a/src/soc/intel/xeon_sp/chip_gen1.c +++ b/src/soc/intel/xeon_sp/chip_gen1.c @@ -27,7 +27,6 @@ static const STACK_RES *domain_to_stack_res(const struct device *dev) static void iio_pci_domain_read_resources(struct device *dev) { - struct resource *res; const STACK_RES *sr = domain_to_stack_res(dev); if (!sr) @@ -37,36 +36,24 @@ static void iio_pci_domain_read_resources(struct device *dev) if (is_domain0(dev)) { /* The 0 - 0xfff IO range is not reported by the HOB but still gets decoded */ - res = new_resource(dev, index++); + struct resource *res = new_resource(dev, index++); res->base = 0; res->size = 0x1000; res->limit = 0xfff; res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; } - if (sr->PciResourceIoBase < sr->PciResourceIoLimit) { - res = new_resource(dev, index++); - res->base = sr->PciResourceIoBase; - res->limit = sr->PciResourceIoLimit; - res->size = res->limit - res->base + 1; - res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED; - } + if (sr->PciResourceIoBase < sr->PciResourceIoLimit) + domain_io_window_from_to(dev, index++, + sr->PciResourceIoBase, sr->PciResourceIoLimit + 1); - if (sr->PciResourceMem32Base < sr->PciResourceMem32Limit) { - res = new_resource(dev, index++); - res->base = sr->PciResourceMem32Base; - res->limit = sr->PciResourceMem32Limit; - res->size = res->limit - res->base + 1; - res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED; - } + if (sr->PciResourceMem32Base < sr->PciResourceMem32Limit) + domain_mem_window_from_to(dev, index++, + sr->PciResourceMem32Base, sr->PciResourceMem32Limit + 1); - if (sr->PciResourceMem64Base < sr->PciResourceMem64Limit) { - res = new_resource(dev, index++); - res->base = sr->PciResourceMem64Base; - res->limit = sr->PciResourceMem64Limit; - res->size = res->limit - res->base + 1; - res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED; - } + if (sr->PciResourceMem64Base < sr->PciResourceMem64Limit) + domain_mem_window_from_to(dev, index++, + sr->PciResourceMem64Base, sr->PciResourceMem64Limit + 1); } /* @@ -129,7 +116,6 @@ void create_cxl_domains(const union xeon_domain_path dp, struct bus *bus, #if CONFIG(SOC_INTEL_HAS_CXL) static void iio_cxl_domain_read_resources(struct device *dev) { - struct resource *res; const STACK_RES *sr = domain_to_stack_res(dev); if (!sr) @@ -137,29 +123,17 @@ static void iio_cxl_domain_read_resources(struct device *dev) int index = 0; - if (sr->IoBase < sr->PciResourceIoBase) { - res = new_resource(dev, index++); - res->base = sr->IoBase; - res->limit = sr->PciResourceIoBase - 1; - res->size = res->limit - res->base + 1; - res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED; - } + if (sr->IoBase < sr->PciResourceIoBase) + domain_io_window_from_to(dev, index++, + sr->IoBase, sr->PciResourceIoBase); - if (sr->Mmio32Base < sr->PciResourceMem32Base) { - res = new_resource(dev, index++); - res->base = sr->Mmio32Base; - res->limit = sr->PciResourceMem32Base - 1; - res->size = res->limit - res->base + 1; - res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED; - } + if (sr->Mmio32Base < sr->PciResourceMem32Base) + domain_mem_window_from_to(dev, index++, + sr->Mmio32Base, sr->PciResourceMem32Base); - if (sr->Mmio64Base < sr->PciResourceMem64Base) { - res = new_resource(dev, index++); - res->base = sr->Mmio64Base; - res->limit = sr->PciResourceMem64Base - 1; - res->size = res->limit - res->base + 1; - res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED; - } + if (sr->Mmio64Base < sr->PciResourceMem64Base) + domain_mem_window_from_to(dev, index++, + sr->Mmio64Base, sr->PciResourceMem64Base); } static struct device_operations iio_cxl_domain_ops = { diff --git a/src/soc/intel/xeon_sp/chip_gen6.c b/src/soc/intel/xeon_sp/chip_gen6.c index a1b1b6504f..c4462d56c9 100644 --- a/src/soc/intel/xeon_sp/chip_gen6.c +++ b/src/soc/intel/xeon_sp/chip_gen6.c @@ -35,20 +35,16 @@ static const UDS_PCIROOT_RES *domain_to_pciroot_res(const struct device *dev) static void iio_pci_domain_read_resources(struct device *dev) { int index = 0; - struct resource *res; const UDS_PCIROOT_RES *pr = domain_to_pciroot_res(dev); /* Initialize the system-wide I/O space constraints. */ - if (pr->IoBase <= pr->IoLimit) { - res = new_resource(dev, index++); - res->base = pr->IoBase; - res->limit = pr->IoLimit; - res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED; - } + if (pr->IoBase <= pr->IoLimit) + domain_io_window_from_to(dev, index++, + pr->IoBase, pr->IoLimit + 1); /* The 0 - 0xfff IO range is not reported by the HOB but still gets decoded */ if (is_domain0(dev)) { - res = new_resource(dev, index++); + struct resource *res = new_resource(dev, index++); res->base = 0; res->limit = 0xfff; res->size = 0x1000; @@ -56,20 +52,14 @@ static void iio_pci_domain_read_resources(struct device *dev) } /* Initialize the system-wide memory resources constraints. */ - if (pr->Mmio32Base <= pr->Mmio32Limit) { - res = new_resource(dev, index++); - res->base = pr->Mmio32Base; - res->limit = pr->Mmio32Limit; - res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED; - } + if (pr->Mmio32Base <= pr->Mmio32Limit) + domain_mem_window_from_to(dev, index++, + pr->Mmio32Base, pr->Mmio32Limit + 1); /* Initialize the system-wide memory resources constraints. */ - if (pr->Mmio64Base <= pr->Mmio64Limit) { - res = new_resource(dev, index++); - res->base = pr->Mmio64Base; - res->limit = pr->Mmio64Limit; - res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED; - } + if (pr->Mmio64Base <= pr->Mmio64Limit) + domain_mem_window_from_to(dev, index++, + pr->Mmio64Base, pr->Mmio64Limit + 1); } static struct device_operations iio_pcie_domain_ops = { diff --git a/src/soc/intel/xeon_sp/spr/ioat.c b/src/soc/intel/xeon_sp/spr/ioat.c index 9ed9576ef3..a0babee5fe 100644 --- a/src/soc/intel/xeon_sp/spr/ioat.c +++ b/src/soc/intel/xeon_sp/spr/ioat.c @@ -61,21 +61,11 @@ static void create_ioat_domain(const union xeon_domain_path dp, struct bus *cons unsigned int index = 0; - if (mem32_base <= mem32_limit) { - struct resource *const res = new_resource(domain, index++); - res->base = mem32_base; - res->limit = mem32_limit; - res->size = res->limit - res->base + 1; - res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED; - } + if (mem32_base <= mem32_limit) + domain_mem_window_from_to(domain, index++, mem32_base, mem32_limit + 1); - if (mem64_base <= mem64_limit) { - struct resource *const res = new_resource(domain, index++); - res->base = mem64_base; - res->limit = mem64_limit; - res->size = res->limit - res->base + 1; - res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED; - } + if (mem64_base <= mem64_limit) + domain_mem_window_from_to(domain, index++, mem64_base, mem64_limit + 1); } void create_ioat_domains(const union xeon_domain_path path, -- cgit v1.2.3