From 4b2464fc90d60f01b0d890e1a0dc6dcdbd119617 Mon Sep 17 00:00:00 2001
From: Felix Held <felix-coreboot@felixheld.de>
Date: Wed, 23 Feb 2022 17:54:20 +0100
Subject: arch/x86: factor out and commonize HPET_BASE_ADDRESS definition

All x86 chipsets and SoCs have the HPET MMIO base address at 0xfed00000,
so define this once in arch/x86 and include this wherever needed. The
old AMD AGESA code in vendorcode that has its own definition is left
unchanged, but sb/amd/cimx/sb800/cfg.c is changed to use the new common
definition.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ifc624051cc6c0f125fa154e826cfbeaf41b4de83
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62304
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
---
 src/soc/intel/xeon_sp/include/soc/iomap.h | 3 ---
 src/soc/intel/xeon_sp/nb_acpi.c           | 1 +
 2 files changed, 1 insertion(+), 3 deletions(-)

(limited to 'src/soc/intel/xeon_sp')

diff --git a/src/soc/intel/xeon_sp/include/soc/iomap.h b/src/soc/intel/xeon_sp/include/soc/iomap.h
index ceaf271eb2..5daf62bf5c 100644
--- a/src/soc/intel/xeon_sp/include/soc/iomap.h
+++ b/src/soc/intel/xeon_sp/include/soc/iomap.h
@@ -26,9 +26,6 @@
 #define VGA_BASE_ADDRESS             0xa0000
 #define VGA_BASE_SIZE                0x20000
 
-/* High Performance Event Timer */
-#define HPET_BASE_ADDRESS            0xfed00000
-
 #define HECI1_BASE_ADDRESS	0xfed1a000
 
 #define PCH_PWRM_BASE_ADDRESS   CONFIG_INTEL_PCH_PWRM_BASE_ADDRESS
diff --git a/src/soc/intel/xeon_sp/nb_acpi.c b/src/soc/intel/xeon_sp/nb_acpi.c
index bb98f0b5fb..0519d4451b 100644
--- a/src/soc/intel/xeon_sp/nb_acpi.c
+++ b/src/soc/intel/xeon_sp/nb_acpi.c
@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-or-later */
 
 #include <acpi/acpigen.h>
+#include <arch/hpet.h>
 #include <assert.h>
 #include <cbmem.h>
 #include <device/mmio.h>
-- 
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