From 3d32f915a9c4d60046574690db966d1f14eebe65 Mon Sep 17 00:00:00 2001 From: Gang Chen Date: Tue, 18 Jun 2024 06:39:12 +0800 Subject: soc/intel/xeon_sp: Reserve PRMRR PRMRR (Protected Region Memory Range Region) are not accessible as normal DRAM regions and needs to be explicitly reserved in memory map. Change-Id: I81d17b1376459510f7c0d43ba4b519b1f2bd3e1f Signed-off-by: Gang Chen Signed-off-by: Shuo Liu Signed-off-by: Jincheng Li Reviewed-on: https://review.coreboot.org/c/coreboot/+/84314 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/soc/intel/xeon_sp/gnr/soc_util.c | 14 ++++++++++++++ src/soc/intel/xeon_sp/include/soc/util.h | 1 + src/soc/intel/xeon_sp/spr/soc_util.c | 5 +++++ src/soc/intel/xeon_sp/uncore.c | 33 ++++++++++++++++++++++++++++++++ 4 files changed, 53 insertions(+) (limited to 'src/soc/intel/xeon_sp') diff --git a/src/soc/intel/xeon_sp/gnr/soc_util.c b/src/soc/intel/xeon_sp/gnr/soc_util.c index 9d8e815f8e..6912809d2d 100644 --- a/src/soc/intel/xeon_sp/gnr/soc_util.c +++ b/src/soc/intel/xeon_sp/gnr/soc_util.c @@ -134,6 +134,20 @@ uint8_t get_cxl_node_count(void) return count; } +unsigned int get_prmrr_count(void) +{ + uint32_t cpu_id = cpu_get_cpuid(); + + switch (cpu_id & CPUID_ALL_STEPPINGS_MASK) { + case CPUID_GRANITERAPIDS: + return 0x7; + case CPUID_SIERRAFOREST: + return 0x4; + default: + return 0; + } +} + bool is_memtype_reserved(uint16_t mem_type) { return false; diff --git a/src/soc/intel/xeon_sp/include/soc/util.h b/src/soc/intel/xeon_sp/include/soc/util.h index 4c7c75fdeb..95d127d825 100644 --- a/src/soc/intel/xeon_sp/include/soc/util.h +++ b/src/soc/intel/xeon_sp/include/soc/util.h @@ -28,6 +28,7 @@ bool is_iio_cxl_stack_res(const xSTACK_RES *res); void bios_done_msr(void *unused); union p2sb_bdf soc_get_hpet_bdf(void); union p2sb_bdf soc_get_ioapic_bdf(void); +unsigned int get_prmrr_count(void); bool get_mmio_high_base_size(resource_t *base, resource_t *size); diff --git a/src/soc/intel/xeon_sp/spr/soc_util.c b/src/soc/intel/xeon_sp/spr/soc_util.c index a6f00c07e0..3b13f53a14 100644 --- a/src/soc/intel/xeon_sp/spr/soc_util.c +++ b/src/soc/intel/xeon_sp/spr/soc_util.c @@ -175,6 +175,11 @@ bool is_memtype_processor_attached(uint16_t mem_type) return (mem_type < MemTypeCxlAccVolatileMem); } +unsigned int get_prmrr_count(void) +{ + return 0x7; +} + bool get_mmio_high_base_size(resource_t *base, resource_t *size) { const IIO_UDS *hob = get_iio_uds(); diff --git a/src/soc/intel/xeon_sp/uncore.c b/src/soc/intel/xeon_sp/uncore.c index c20e55fdce..1d77675aeb 100644 --- a/src/soc/intel/xeon_sp/uncore.c +++ b/src/soc/intel/xeon_sp/uncore.c @@ -4,8 +4,10 @@ #include #include #include +#include #include #include +#include #include #include #include @@ -154,6 +156,29 @@ static void configure_dpr(struct device *dev) #define MC_DRAM_RESOURCE_MMIO_HIGH 0x1000 #define MC_DRAM_RESOURCE_ANON_START 0x1001 +__weak unsigned int get_prmrr_count(void) +{ + return 0x0; +} + +static bool get_prmrr_region(unsigned int msr_addr, uint64_t *base, uint64_t *size) +{ + /* Check if processor supports PRMRR */ + msr_t msr1 = rdmsr(MTRR_CAP_MSR); + if (!(msr1.lo & MTRR_CAP_PRMRR)) { + printk(BIOS_ERR, "%s(): PRMRR is not supported.\n", __func__); + return false; + } + + /* Mask out bits 0-11 to get the base address */ + *base = msr_read(msr_addr) & ~((1 << RANGE_SHIFT) - 1); + + uint64_t mask = msr_read(MSR_PRMRR_PHYS_MASK); + *size = calculate_var_mtrr_size(mask); + + return (*base && *size); +} + /* * Host Memory Map: * @@ -302,6 +327,14 @@ static void mc_add_dram_resources(struct device *dev, int *res_count) LOG_RESOURCE("high_ram", dev, res); } + uint64_t prmrr_base, prmrr_size; + for (unsigned int i = 0; i < get_prmrr_count(); i++) { + if (get_prmrr_region(MSR_PRMRR_BASE(i), &prmrr_base, &prmrr_size)) { + res = reserved_ram_range(dev, index++, prmrr_base, prmrr_size); + LOG_RESOURCE("prmrr", dev, res); + } + } + if (CONFIG(SOC_INTEL_HAS_CXL)) { /* CXL Memory */ uint8_t i; -- cgit v1.2.3