From 3a79633920850cb1d44f515a9cfe8372c6c01341 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Fri, 22 Oct 2021 22:38:21 +0200 Subject: soc/*/Makefile: don't add cpu/x86/cache No SoC uses the ramstage-only x86_enable_cache helper function to call enable_cache with some added port 0x80 and console output. Signed-off-by: Felix Held Suggested-by: Angel Pons Change-Id: I7c5039e1341fd4089078ad7ffb2fe6584a94045c Reviewed-on: https://review.coreboot.org/c/coreboot/+/58547 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Marshall Dawson --- src/soc/intel/xeon_sp/skx/Makefile.inc | 1 - 1 file changed, 1 deletion(-) (limited to 'src/soc/intel/xeon_sp') diff --git a/src/soc/intel/xeon_sp/skx/Makefile.inc b/src/soc/intel/xeon_sp/skx/Makefile.inc index eafd800229..b0714d4ef7 100644 --- a/src/soc/intel/xeon_sp/skx/Makefile.inc +++ b/src/soc/intel/xeon_sp/skx/Makefile.inc @@ -5,7 +5,6 @@ ifeq ($(CONFIG_SOC_INTEL_SKYLAKE_SP),y) subdirs-y += ../../../../cpu/intel/microcode subdirs-y += ../../../../cpu/intel/turbo subdirs-y += ../../../../cpu/x86/lapic -subdirs-y += ../../../../cpu/x86/cache postcar-y += soc_util.c -- cgit v1.2.3