From 2ccc0a4d9fc91a57e1dec8913e6d999402e927a2 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Thu, 25 Mar 2021 20:01:47 +0530 Subject: soc/intel: Rename and move MISCCFG_GPIO_PM_CONFIG_BITS definition to soc/gpio.h Lists of changes: 1. Rename MISCCFG_ENABLE_GPIO_PM_CONFIG -> MISCCFG_GPIO_PM_CONFIG_BITS 2. Move MISCCFG_GPIO_PM_CONFIG_BITS definition from intelblock/gpio.h to soc/gpio.h. Refer to detailed description below to understand the motivation behind this change. An advanced GPIO PM capabilities has been introduced since CNP PCH, refer to 'include/intelblock/gpio.h' for detailed GPIO PM bit definitions. Now with TGP PCH, additional bits are defined in the MISCCFG register for GPIO PM control. This results in different SoCs supporting different number of bits. The bits defined in earlier platforms (CNL, CML, ICL) are present on TGL, JSL and ADL too. Hence, refactor the common GPIO code to keep the bit definitions in intelblock/gpio.h, but the definition of MISCCFG_GPIO_PM_CONFIG_BITS is moved to soc/gpio.h so that each SoC can provide this as per hardware support. TEST=On ADL, TGL and JSL platform. Without this CL : GPIO COMM 0 MISCCFG:0xC0 (Bit 6 and 7 enable) With this CL : GPIO COMM 0 MISCCFG: 0x00 (Bit 6 and 7 disable) Change-Id: Ie027cbd7b99b39752941384339a34f8995c10c94 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/51767 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/soc/intel/xeon_sp/include/soc/gpio.h | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'src/soc/intel/xeon_sp') diff --git a/src/soc/intel/xeon_sp/include/soc/gpio.h b/src/soc/intel/xeon_sp/include/soc/gpio.h index 6e85d4e021..04eb9ae31c 100644 --- a/src/soc/intel/xeon_sp/include/soc/gpio.h +++ b/src/soc/intel/xeon_sp/include/soc/gpio.h @@ -6,4 +6,10 @@ #include #include +/* + * XEON SP series doesn't support dynamic GPIO PM hence GPIO community + * MISCCFG register doesn't have PM bits + */ +#define MISCCFG_GPIO_PM_CONFIG_BITS 0 + #endif -- cgit v1.2.3