From 12bee2af237afb6736a91d3f526789efb0542aeb Mon Sep 17 00:00:00 2001 From: Johnny Lin Date: Tue, 4 Aug 2020 18:01:54 +0800 Subject: xeon_sp/cpx: Enable HWP Intel Speed Shift Set HWP base feature, enable EPP, lock thermal interrupt and lock MSR Tested=On OCP Delta Lake, rdmsr 0x1aa shows 403040 Change-Id: I6d23de4032562095db1aaf96ddfd2b70a4517faa Signed-off-by: Johnny Lin Reviewed-on: https://review.coreboot.org/c/coreboot/+/44171 Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/soc/intel/xeon_sp/cpx/cpu.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'src/soc/intel/xeon_sp') diff --git a/src/soc/intel/xeon_sp/cpx/cpu.c b/src/soc/intel/xeon_sp/cpx/cpu.c index 1df5c1350c..cf903b872a 100644 --- a/src/soc/intel/xeon_sp/cpx/cpu.c +++ b/src/soc/intel/xeon_sp/cpx/cpu.c @@ -64,6 +64,18 @@ static void each_cpu_init(struct device *cpu) __func__, dev_path(cpu), cpu_index(), cpu->path.apic.apic_id); setup_lapic(); + /* + * Set HWP base feature, EPP reg enumeration, lock thermal and msr + * This is package level MSR. Need to check if it updates correctly on + * multi-socket platform. + */ + msr = rdmsr(MSR_MISC_PWR_MGMT); + if (!(msr.lo & LOCK_MISC_PWR_MGMT_MSR)) { /* if already locked skip update */ + msr.lo = (HWP_ENUM_ENABLE | HWP_EPP_ENUM_ENABLE | LOCK_MISC_PWR_MGMT_MSR | + LOCK_THERM_INT); + wrmsr(MSR_MISC_PWR_MGMT, msr); + } + /* Enable Fast Strings */ msr = rdmsr(IA32_MISC_ENABLE); msr.lo |= FAST_STRINGS_ENABLE_BIT; -- cgit v1.2.3