From 0a12d2bdc848098b6f44f75b9289931405cb53b4 Mon Sep 17 00:00:00 2001
From: Naresh Solanki <Naresh.Solanki@9elements.com>
Date: Mon, 17 Jul 2023 15:52:55 +0200
Subject: soc/intel/xeon/spr: Improve RMT configuration

Set AllowedSocketsInParallel to 1 for RMT builds.
This help in associating any failures encountered during RMT run
with the corresponding Socket/MC/DIMM.

Intel recommended setting EnforcePopulationPor to 1 for RMT runs
for debugging failures if any.

Change-Id: Ie2301368e9470cc23171c3c4eca9fe978e1513d4
Signed-off-by: Naresh Solanki <Naresh.Solanki@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76679
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
---
 src/soc/intel/xeon_sp/spr/romstage.c | 2 ++
 1 file changed, 2 insertions(+)

(limited to 'src/soc/intel/xeon_sp')

diff --git a/src/soc/intel/xeon_sp/spr/romstage.c b/src/soc/intel/xeon_sp/spr/romstage.c
index 8004730c59..0443df1f60 100644
--- a/src/soc/intel/xeon_sp/spr/romstage.c
+++ b/src/soc/intel/xeon_sp/spr/romstage.c
@@ -223,6 +223,8 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
 		mupd->FspmConfig.EnableRMT = 0x1;
 		/* Set FSP debug message to Max for RMT logs */
 		mupd->FspmConfig.serialDebugMsgLvl = 0x3;
+		mupd->FspmConfig.AllowedSocketsInParallel = 0x1;
+		mupd->FspmConfig.EnforcePopulationPor = 0x1;
 	}
 }
 
-- 
cgit v1.2.3