From f4721246db125e08b5e60a8a38a08cb92c478bd3 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Thu, 19 Nov 2020 16:20:27 +0100 Subject: soc/intel/xeon_sp: Select INTEL_COMMON_BLOCK_TCO TCO is configured by FSP. This mostly makes it possible to report TCO events in SMM if enabled. Change-Id: I4f81c7888e45ed01ee68b1d6e6a9986a4d735467 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/47764 Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/soc/intel/xeon_sp/pmc.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) (limited to 'src/soc/intel/xeon_sp/pmc.c') diff --git a/src/soc/intel/xeon_sp/pmc.c b/src/soc/intel/xeon_sp/pmc.c index a418ae5bab..b4f86db20a 100644 --- a/src/soc/intel/xeon_sp/pmc.c +++ b/src/soc/intel/xeon_sp/pmc.c @@ -193,3 +193,25 @@ const char *const *soc_smi_sts_array(size_t *smi_arr) *smi_arr = ARRAY_SIZE(smi_sts_bits); return smi_sts_bits; } + +const char *const *soc_tco_sts_array(size_t *tco_arr) +{ + static const char *const tco_sts_bits[] = { + [0] = "NMI2SMI", + [1] = "OS_TCO", + [2] = "TCO_INT", + [3] = "TIMEOUT", + [7] = "NEWCENTURY", + [8] = "BIOSWR", + [9] = "CPUSCI", + [10] = "CPUSMI", + [12] = "CPUSERR", + [13] = "SLVSEL", + [16] = "INTRD_DET", + [17] = "SECOND_TO", + [20] = "SMLINK_SLV" + }; + + *tco_arr = ARRAY_SIZE(tco_sts_bits); + return tco_sts_bits; +} -- cgit v1.2.3