From 3d51e833478005196b5e0e01bb60878a76274a3d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Mon, 21 Nov 2022 12:51:20 +0100 Subject: soc/intel/*/include/soc/pmc.h: Add missing periodic SMI rate bits MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Based on: - Apollo Lake datasheet Vol. 3 Revision 005: https://cdrdv2.intel.com/v1/dl/getContent/334819 - 7th Generation Intel Processor Families I/O for U/Y Platforms Datasheet Vol.2 August 2017: https://cdrdv2.intel.com/v1/dl/getContent/334659 - edk2-platforms source for Whitley and Purley platforms (Xeon SP) Signed-off-by: Michał Żygowski Change-Id: Ic600d39d49135808dd1f571c9eff3cdb98682796 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69871 Tested-by: build bot (Jenkins) Reviewed-by: Krystian Hebel --- src/soc/intel/xeon_sp/lbg/include/soc/pmc.h | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'src/soc/intel/xeon_sp/lbg') diff --git a/src/soc/intel/xeon_sp/lbg/include/soc/pmc.h b/src/soc/intel/xeon_sp/lbg/include/soc/pmc.h index d49986339c..88a9b10606 100644 --- a/src/soc/intel/xeon_sp/lbg/include/soc/pmc.h +++ b/src/soc/intel/xeon_sp/lbg/include/soc/pmc.h @@ -25,6 +25,11 @@ #define MS4V (1 << 18) #define GBL_RST_STS (1 << 16) #define SMI_LOCK (1 << 4) +#define PER_SMI_SEL_MASK (3 << 1) +#define SMI_RATE_64S (0 << 1) +#define SMI_RATE_32S (1 << 1) +#define SMI_RATE_16S (2 << 1) +#define SMI_RATE_8S (3 << 1) #define GEN_PMCON_B 0xa4 #define SLP_STR_POL_LOCK (1 << 18) #define ACPI_BASE_LOCK (1 << 17) -- cgit v1.2.3