From ea643a81a10d3d3d308ec3d734958193474f555d Mon Sep 17 00:00:00 2001 From: David Hendricks Date: Sat, 4 Mar 2023 16:19:35 -0800 Subject: soc/intel/xeon_sp: Add PM definition for SPR-SP Change-Id: I13ed156a1b967e87fa30b1867feed03c3d17b992 Signed-off-by: Jonathan Zhang Signed-off-by: David Hendricks Reviewed-on: https://review.coreboot.org/c/coreboot/+/72613 Tested-by: build bot (Jenkins) Reviewed-by: Jonathan Zhang --- src/soc/intel/xeon_sp/lbg/include/soc/soc_pm.h | 13 +++++++++++++ 1 file changed, 13 insertions(+) create mode 100644 src/soc/intel/xeon_sp/lbg/include/soc/soc_pm.h (limited to 'src/soc/intel/xeon_sp/lbg/include') diff --git a/src/soc/intel/xeon_sp/lbg/include/soc/soc_pm.h b/src/soc/intel/xeon_sp/lbg/include/soc/soc_pm.h new file mode 100644 index 0000000000..2e309b5928 --- /dev/null +++ b/src/soc/intel/xeon_sp/lbg/include/soc/soc_pm.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef _SOC_LBG_PM_H_ +#define _SOC_LBG_PM_H_ + +#define GPE0_STS(x) (0x80 + ((x) * 4)) +#define GPE0_EN(x) (0x90 + ((x) * 4)) + +/* This is defined as ETR3 in EDS. We named it as ETR here for consistency */ +#define ETR 0xac +#define PRSTS 0x10 + +#endif /* _SOC_LBG_PM_H_ */ -- cgit v1.2.3