From f4721246db125e08b5e60a8a38a08cb92c478bd3 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Thu, 19 Nov 2020 16:20:27 +0100 Subject: soc/intel/xeon_sp: Select INTEL_COMMON_BLOCK_TCO TCO is configured by FSP. This mostly makes it possible to report TCO events in SMM if enabled. Change-Id: I4f81c7888e45ed01ee68b1d6e6a9986a4d735467 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/47764 Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/soc/intel/xeon_sp/include/soc/smbus.h | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) create mode 100644 src/soc/intel/xeon_sp/include/soc/smbus.h (limited to 'src/soc/intel/xeon_sp/include') diff --git a/src/soc/intel/xeon_sp/include/soc/smbus.h b/src/soc/intel/xeon_sp/include/soc/smbus.h new file mode 100644 index 0000000000..00aae2cbe8 --- /dev/null +++ b/src/soc/intel/xeon_sp/include/soc/smbus.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_SMBUS_H_ +#define _SOC_SMBUS_H_ + +/* TCO registers and fields live behind TCOBASE I/O bar in SMBus device. */ +#define TCO1_STS 0x04 +#define TCO_TIMEOUT (1 << 3) +#define TCO2_STS 0x06 +#define TCO_STS_SECOND_TO (1 << 1) +#define TCO_INTRD_DET (1 << 0) +#define TCO1_CNT 0x08 +#define TCO_LOCK (1 << 12) +#define TCO_TMR_HLT (1 << 11) +#define TCO2_CNT 0x0A +#define TCO_INTRD_SEL_MASK (3 << 1) +#define TCO_INTRD_SEL_SMI (1 << 2) +#define TCO_INTRD_SEL_INT (1 << 1) + +/* SMBus I/O bits. */ +#define SMBUS_SLAVE_ADDR 0x24 + +#endif -- cgit v1.2.3