From 0f91e9ce5f53db70bf738f66988603156021d7c7 Mon Sep 17 00:00:00 2001
From: Arthur Heymans <arthur@aheymans.xyz>
Date: Fri, 16 Oct 2020 13:15:50 +0200
Subject: soc/intel/xeon_sp/cpx: Lock down P2SB SBI

This is required for CBnT.

Change-Id: Idfd5c01003e0d307631e5c6895ac02e89a9aff08
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46499
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/intel/xeon_sp/include/soc/p2sb.h | 3 +++
 1 file changed, 3 insertions(+)

(limited to 'src/soc/intel/xeon_sp/include')

diff --git a/src/soc/intel/xeon_sp/include/soc/p2sb.h b/src/soc/intel/xeon_sp/include/soc/p2sb.h
index 336befee60..3bdd4530ca 100644
--- a/src/soc/intel/xeon_sp/include/soc/p2sb.h
+++ b/src/soc/intel/xeon_sp/include/soc/p2sb.h
@@ -11,3 +11,6 @@
 #define HPTC_ADDR_ENABLE_BIT		(1 << 7)
 #define PCH_P2SB_EPMASK0		0xb0
 #define P2SB_SIZE			(16 * MiB)
+
+#define P2SBC				0xe0
+#define SBILOCK				(1 << 31)
-- 
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