From 204ffcb98d5594983aed047ec2430e0b6aa515a0 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Wed, 5 Jul 2023 12:12:25 +0200 Subject: soc/intel/xeon_sp/ebg: Add periodic SMI bits definition MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: Ia906a115538964628958bb4b6e3de3aa71577cce Signed-off-by: Michał Żygowski Reviewed-on: https://review.coreboot.org/c/coreboot/+/76252 Reviewed-by: Martin L Roth Tested-by: build bot (Jenkins) --- src/soc/intel/xeon_sp/ebg/include/soc/pmc.h | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'src/soc/intel/xeon_sp/ebg/include') diff --git a/src/soc/intel/xeon_sp/ebg/include/soc/pmc.h b/src/soc/intel/xeon_sp/ebg/include/soc/pmc.h index 5f80503a61..4362ce5eff 100644 --- a/src/soc/intel/xeon_sp/ebg/include/soc/pmc.h +++ b/src/soc/intel/xeon_sp/ebg/include/soc/pmc.h @@ -14,6 +14,11 @@ #define SUS_PWR_FLR (1 << 16) #define PWR_FLR (1 << 14) #define HOST_RST_STS (1 << 9) +#define PER_SMI_SEL_MASK (3 << 1) +#define SMI_RATE_64S (0 << 1) +#define SMI_RATE_32S (1 << 1) +#define SMI_RATE_16S (2 << 1) +#define SMI_RATE_8S (3 << 1) #define SLEEP_AFTER_POWER_FAIL (1 << 0) #define GEN_PMCON_B 0x1024 #define SLP_STR_POL_LOCK (1 << 18) -- cgit v1.2.3