From 7a5c3696140dc839cb709adc3ebac58821efd786 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Mon, 4 Jan 2021 12:49:39 +0100 Subject: soc/intel/xeon_sp/cpx: Account for 'rc' heap manager The xeon_sp/cpx has a second 'rc' heap inside FSP-M that is statically allocated at the start of CAR. This breaks FSP 2.0 specification. This can be worked around in the linker scripts to make sure coreboot and FSP-M don't fight over the same memory. Tested - on ocp/deltalake: boot and the "Smashed stack detected in romstage!" message at the end of romstage is gone. - qemu/i440fx: BUILD_TIMELESS=1 results in the same binary. Change-Id: I6d02b8a46a2a8ef00f34d8f257595d43f5d3d590 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/49085 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Jonathan Zhang --- src/soc/intel/xeon_sp/cpx/Kconfig | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) (limited to 'src/soc/intel/xeon_sp/cpx') diff --git a/src/soc/intel/xeon_sp/cpx/Kconfig b/src/soc/intel/xeon_sp/cpx/Kconfig index 7b583cd14a..ded69987ea 100644 --- a/src/soc/intel/xeon_sp/cpx/Kconfig +++ b/src/soc/intel/xeon_sp/cpx/Kconfig @@ -43,13 +43,22 @@ config DCACHE_RAM_SIZE config DCACHE_BSP_STACK_SIZE hex - default 0x140000 + default 0x40000 help The amount of anticipated stack usage in CAR by bootblock and other stages. It needs to include FSP-M stack requirement and CB romstage stack requirement. The integration documentation - says this needs to be 256KiB, but practice show this needs to - be a lot more. + says this needs to be 256KiB. + +config FSP_M_RC_HEAP_SIZE + hex + default 0x130000 + help + On xeon_sp/cpx FSP-M has two separate heap managers, one regular + whose size and base are controllable via the StackBase and + StackSize UPDs and a 'rc' heap manager that is statically + allocated at 0xfe800000 (the CAR base) and consumes about 0x130000 + bytes of memory. config CPU_MICROCODE_CBFS_LOC hex -- cgit v1.2.3