From 3d802535cbf222d403e0d7d5cc6632546333a4c4 Mon Sep 17 00:00:00 2001
From: Arthur Heymans <arthur@aheymans.xyz>
Date: Thu, 12 Nov 2020 21:17:56 +0100
Subject: soc/intel/xeon_sp: Set coreboot defined IOAPIC and HPET BDF

Don't rely on the FSP-S setting the HPET and IOAPIC BDF. This makes
coreboot in control of these settings.

Change-Id: I937ebf05533019cb1a2be771ef3b9193a458dddf
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47537
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
---
 src/soc/intel/xeon_sp/cpx/chip.c | 2 ++
 1 file changed, 2 insertions(+)

(limited to 'src/soc/intel/xeon_sp/cpx')

diff --git a/src/soc/intel/xeon_sp/cpx/chip.c b/src/soc/intel/xeon_sp/cpx/chip.c
index b7752b25cd..6beebdf925 100644
--- a/src/soc/intel/xeon_sp/cpx/chip.c
+++ b/src/soc/intel/xeon_sp/cpx/chip.c
@@ -10,6 +10,7 @@
 #include <soc/acpi.h>
 #include <soc/chip_common.h>
 #include <soc/cpu.h>
+#include <soc/pch.h>
 #include <soc/ramstage.h>
 #include <soc/p2sb.h>
 #include <soc/soc_util.h>
@@ -76,6 +77,7 @@ static void chip_init(void *data)
 {
 	printk(BIOS_DEBUG, "coreboot: calling fsp_silicon_init\n");
 	fsp_silicon_init(false);
+	override_hpet_ioapic_bdf();
 	pch_enable_ioapic();
 	setup_lapic();
 	p2sb_unhide();
-- 
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