From 2560ad3233a2212a5346755137c9a333df14d004 Mon Sep 17 00:00:00 2001 From: Marc Jones Date: Mon, 28 Sep 2020 15:23:35 -0600 Subject: soc/intel/xeon_sp/cpx: Add soc_acpi_fill_fadt() Prepare for common ACPI code. Make acpi_fill_fadt() match intel/commom/block/acpi/acpi.c function. Use soc_acpi_fill_fadt() to set cpx fadt->flags. Change-Id: I9c04dd478aa5e0f1467e63d06da094128edd9650 Signed-off-by: Marc Jones Reviewed-on: https://review.coreboot.org/c/coreboot/+/45845 Reviewed-by: Stefan Reinauer Reviewed-by: Jay Talbott Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/soc/intel/xeon_sp/cpx/acpi.c | 28 ++++++++++++++++++---------- src/soc/intel/xeon_sp/cpx/soc_acpi.c | 7 +++++++ 2 files changed, 25 insertions(+), 10 deletions(-) (limited to 'src/soc/intel/xeon_sp/cpx') diff --git a/src/soc/intel/xeon_sp/cpx/acpi.c b/src/soc/intel/xeon_sp/cpx/acpi.c index a1ebc4ae92..8d3e86a10b 100644 --- a/src/soc/intel/xeon_sp/cpx/acpi.c +++ b/src/soc/intel/xeon_sp/cpx/acpi.c @@ -130,13 +130,18 @@ unsigned long acpi_fill_madt(unsigned long current) void acpi_fill_fadt(acpi_fadt_t *fadt) { - const uint16_t pmbase = ACPI_BASE_ADDRESS; fadt->header.revision = get_acpi_table_revision(FADT); fadt->sci_int = acpi_sci_irq(); + if (permanent_smi_handler()) { + fadt->smi_cmd = APM_CNT; + fadt->acpi_enable = APM_CNT_ACPI_ENABLE; + fadt->acpi_disable = APM_CNT_ACPI_DISABLE; + } + fadt->pm1a_evt_blk = pmbase + PM1_STS; fadt->pm1a_cnt_blk = pmbase + PM1_CNT; @@ -151,26 +156,29 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) fadt->duty_offset = 1; fadt->day_alrm = 0xd; - fadt->flags |= ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | ACPI_FADT_C2_MP_SUPPORTED | + fadt->flags |= ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | + ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON | + ACPI_FADT_SEALED_CASE | ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK; fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8; fadt->x_pm1a_evt_blk.addrl = pmbase + PM1_STS; + fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; fadt->x_pm1a_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_pm1a_cnt_blk.bit_width = fadt->pm1_cnt_len * 8; fadt->x_pm1a_cnt_blk.addrl = pmbase + PM1_CNT; + fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; - if (permanent_smi_handler()) { - fadt->smi_cmd = APM_CNT; - fadt->acpi_enable = APM_CNT_ACPI_ENABLE; - fadt->acpi_disable = APM_CNT_ACPI_DISABLE; - } - - /* General-Purpose Event Registers */ + /* + * Windows 10 requires x_gpe0_blk to be set starting with FADT revision 5. + * The bit_width field intentionally overflows here. + * The OSPM can instead use the values in `fadt->gpe0_blk{,_len}`, which + * seems to work fine on Linux 5.0 and Windows 10. + */ fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_gpe0_blk.bit_width = 64; /* EventStatus + EventEnable */ + fadt->x_gpe0_blk.bit_width = fadt->gpe0_blk_len * 8; fadt->x_gpe0_blk.bit_offset = 0; fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; fadt->x_gpe0_blk.addrl = fadt->gpe0_blk; diff --git a/src/soc/intel/xeon_sp/cpx/soc_acpi.c b/src/soc/intel/xeon_sp/cpx/soc_acpi.c index db1d3d2bd2..d0b82e57db 100644 --- a/src/soc/intel/xeon_sp/cpx/soc_acpi.c +++ b/src/soc/intel/xeon_sp/cpx/soc_acpi.c @@ -52,6 +52,13 @@ uint32_t soc_read_sci_irq_select(void) return pci_read_config32(dev, PMC_ACPI_CNT); } +void soc_fill_fadt(acpi_fadt_t *fadt) +{ + /* Clear flags set by common/block/acpi/acpi.c acpi_fill_fadt() */ + fadt->flags &= ~(ACPI_FADT_SLEEP_BUTTON | ACPI_FADT_SEALED_CASE | + ACPI_FADT_S4_RTC_WAKE); +} + /* * Currently called in southbridge_inject_dsdt(). Change to soc_southbridge_inject_dsdt() * with a call from the common/function or find another way to call this at the correct place -- cgit v1.2.3