From 0ccb3828bc6464dc51ef5075d9cc050272e0f75a Mon Sep 17 00:00:00 2001 From: Jonathan Zhang Date: Wed, 8 Jul 2020 14:26:55 -0700 Subject: vendocode/intel/fsp/fsp2_0/cpx_sp: Update to FSP ww28 release and adapt soc CPX-SP FSP ww28 release adds UPDs to allow enablement of VT-d and VMX. Also update IIO UDS HOB definition file accordingly. Intel CPX-SP FSP has been using FSPM_CONFIG intead of FSP_M_CONFIG. Other Intel FSPs have been using FSP_M_CONFIG. The feedback from Intel is that they will converge to use FSPM_CONFIG over time. So both will co-exist for some time. Today coreboot common code expects FSP_M_CONFIG. Accomodate this situation in FspmUpd.h. The CPX-SP soc code is updated accordingly. Signed-off-by: Jonathan Zhang Change-Id: If6d0a041eaad9eb2f811e74d219fff1cc38e95a4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43315 Tested-by: build bot (Jenkins) Reviewed-by: Christian Walter --- src/soc/intel/xeon_sp/cpx/upd_display.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/soc/intel/xeon_sp/cpx/upd_display.c') diff --git a/src/soc/intel/xeon_sp/cpx/upd_display.c b/src/soc/intel/xeon_sp/cpx/upd_display.c index d3222e65f0..ae5eeda09c 100644 --- a/src/soc/intel/xeon_sp/cpx/upd_display.c +++ b/src/soc/intel/xeon_sp/cpx/upd_display.c @@ -12,8 +12,8 @@ void soc_display_fspm_upd_params( const FSPM_UPD *fspm_old_upd, const FSPM_UPD *fspm_new_upd) { - const FSP_M_CONFIG *new; - const FSP_M_CONFIG *old; + const FSPM_CONFIG *new; + const FSPM_CONFIG *old; old = &fspm_old_upd->FspmConfig; new = &fspm_new_upd->FspmConfig; -- cgit v1.2.3