From 2e410757efb824555191d8afd78cf79ab5ba6049 Mon Sep 17 00:00:00 2001 From: Andrey Petrov Date: Fri, 20 Mar 2020 12:08:32 -0700 Subject: soc/intel/xeon_sp: Add basic Cooperlake-SP support This adds barebones support. What works: * Linux kernel boots fine * SIRQ and PCH interupts work fine (only in IOAPIC mode) * PCH devices are usable What doesn't: * MP init is not there yet, only 1 CPU is up * SMM is not supported * GPIO is not available * All IIO and extended bus numbers enumeration is not yet available * Warm reset flow is untested * MRC cache save/load TEST=boots into Linux Signed-off-by: Andrey Petrov Change-Id: I7c987badc3c53f16ad178369c7e0906d6596e465 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39713 Reviewed-by: Maxim Polyakov Tested-by: build bot (Jenkins) --- src/soc/intel/xeon_sp/cpx/romstage.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) create mode 100644 src/soc/intel/xeon_sp/cpx/romstage.c (limited to 'src/soc/intel/xeon_sp/cpx/romstage.c') diff --git a/src/soc/intel/xeon_sp/cpx/romstage.c b/src/soc/intel/xeon_sp/cpx/romstage.c new file mode 100644 index 0000000000..32ada9f4cb --- /dev/null +++ b/src/soc/intel/xeon_sp/cpx/romstage.c @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include +#include +#include "chip.h" + +void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) +{ + FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; + + (void)m_cfg; +} -- cgit v1.2.3