From 7919d618f8ffd742df1e5d4804656b20412f4999 Mon Sep 17 00:00:00 2001 From: Jonathan Zhang Date: Thu, 2 Apr 2020 17:27:54 -0700 Subject: soc/intel/xeon_sp/cpx: add chip operation and PCIe enumeration Add PCIe enumeration and resource assignment/allocation. Xeon-SP processor family has split IIO design, where PCIe domain 0 is split into multiple stacks. Each stack has its own resource ranges (eg. IO resource, mem32 resource, mem64 resource). The stack itself is not PCIe device, it does not have config space to be probed/programmed. The stack is programmed by FSP. coreboot needs to take into account of stack when doing PCIe enumeration and resource allocation. Current coreboot PCIe resource allocator does not support the concept of split IIO stack, thus entire support is done locally in this patch. In near future, improvements will be done, first generalize for xeon-sp, then generalize for coreboot PCIe device code. Signed-off-by: Jonathan Zhang Signed-off-by: Reddy Chagam Change-Id: If461b1dc1f313d98b676dc9e91d08a1dbb9cb388 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40110 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin Reviewed-by: Philipp Deppenwiese --- src/soc/intel/xeon_sp/cpx/include/soc/irq.h | 8 +++++++- src/soc/intel/xeon_sp/cpx/include/soc/soc_util.h | 25 ++++++++++++++++++++++++ 2 files changed, 32 insertions(+), 1 deletion(-) create mode 100644 src/soc/intel/xeon_sp/cpx/include/soc/soc_util.h (limited to 'src/soc/intel/xeon_sp/cpx/include') diff --git a/src/soc/intel/xeon_sp/cpx/include/soc/irq.h b/src/soc/intel/xeon_sp/cpx/include/soc/irq.h index 71e058417e..efd50577b6 100644 --- a/src/soc/intel/xeon_sp/cpx/include/soc/irq.h +++ b/src/soc/intel/xeon_sp/cpx/include/soc/irq.h @@ -1,3 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -/* nothing here, please come back later */ +#ifndef _SOC_IRQ_H_ +#define _SOC_IRQ_H_ + +#define PCH_IRQ10 10 +#define PCH_IRQ11 11 + +#endif /* _SOC_IRQ_H_ */ diff --git a/src/soc/intel/xeon_sp/cpx/include/soc/soc_util.h b/src/soc/intel/xeon_sp/cpx/include/soc/soc_util.h new file mode 100644 index 0000000000..d8b038c4d5 --- /dev/null +++ b/src/soc/intel/xeon_sp/cpx/include/soc/soc_util.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_UTIL_H_ +#define _SOC_UTIL_H_ + +#include +#include +#include +#include + +#define DEV_FUNC_ENTER(dev) \ + printk(BIOS_SPEW, "%s:%s:%d: ENTER (dev: %s)\n", \ + __FILE__, __func__, __LINE__, dev_path(dev)) + +#define DEV_FUNC_EXIT(dev) \ + printk(BIOS_SPEW, "%s:%s:%d: EXIT (dev: %s)\n", __FILE__, \ + __func__, __LINE__, dev_path(dev)) + +struct iiostack_resource { + uint8_t no_of_stacks; + STACK_RES res[MAX_SOCKET * MAX_LOGIC_IIO_STACK]; +}; + +uint8_t get_iiostack_info(struct iiostack_resource *info); +#endif /* _SOC_UTIL_H_ */ -- cgit v1.2.3