From dddb9a85bd1e9810410f14010f20c9ce2dabfee5 Mon Sep 17 00:00:00 2001 From: Andrey Petrov Date: Mon, 20 Apr 2020 18:07:08 -0700 Subject: soc/intel/xeon_sp/cpx: Work around FSP-M issues Currently FSP-M does not implement the spec completely, e.g it is unable to use user-provided heap location in CAR. While this is being resolved, this workaround is a stop-gap solution that allows multi-socket usage. TEST=tested on OCP Sonora Pass EVT and Intel Cedar Island CRB Change-Id: Ia2529526a8724cf54377b0bd2339b04fa900815a Signed-off-by: Andrey Petrov Reviewed-on: https://review.coreboot.org/c/coreboot/+/40555 Reviewed-by: Maxim Polyakov Tested-by: build bot (Jenkins) --- src/soc/intel/xeon_sp/cpx/cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/soc/intel/xeon_sp/cpx/cpu.c') diff --git a/src/soc/intel/xeon_sp/cpx/cpu.c b/src/soc/intel/xeon_sp/cpx/cpu.c index 8824686674..a62c2f0318 100644 --- a/src/soc/intel/xeon_sp/cpx/cpu.c +++ b/src/soc/intel/xeon_sp/cpx/cpu.c @@ -28,7 +28,7 @@ const void *intel_mp_current_microcode(void) static void each_cpu_init(struct device *cpu) { - printk(BIOS_INFO, "%s dev: %s, cpu: %d, apic_id: 0x%x\n", + printk(BIOS_SPEW, "%s dev: %s, cpu: %d, apic_id: 0x%x\n", __func__, dev_path(cpu), cpu_index(), cpu->path.apic.apic_id); setup_lapic(); -- cgit v1.2.3