From 53b465d1c19502776853c236dbc7afb2c53f0c87 Mon Sep 17 00:00:00 2001 From: Marc Jones Date: Thu, 15 Oct 2020 15:16:45 -0600 Subject: soc/intel/xeon_sp: Move read_msr_ppin() to common util.c Move CPX and SKX read_msr_ppin() to common util.c file. Update drivers/ocp/smbios #include to match. Change-Id: I4c4281d2d5ce679f5444a502fa88df04de9f2cd8 Signed-off-by: Marc Jones Reviewed-on: https://review.coreboot.org/c/coreboot/+/46479 Tested-by: build bot (Jenkins) Reviewed-by: Jay Talbott Reviewed-by: Arthur Heymans Reviewed-by: Stefan Reinauer --- src/soc/intel/xeon_sp/cpx/cpu.c | 31 ------------------------------- 1 file changed, 31 deletions(-) (limited to 'src/soc/intel/xeon_sp/cpx/cpu.c') diff --git a/src/soc/intel/xeon_sp/cpx/cpu.c b/src/soc/intel/xeon_sp/cpx/cpu.c index 4afe47cbff..5bde819ec6 100644 --- a/src/soc/intel/xeon_sp/cpx/cpu.c +++ b/src/soc/intel/xeon_sp/cpx/cpu.c @@ -205,34 +205,3 @@ void cpx_init_cpus(struct device *dev) /* update numa domain for all cpu devices */ xeonsp_init_cpu_config(); } - -msr_t read_msr_ppin(void) -{ - msr_t ppin = {0}; - msr_t msr; - - /* If MSR_PLATFORM_INFO PPIN_CAP is 0, PPIN capability is not supported */ - msr = rdmsr(MSR_PLATFORM_INFO); - if ((msr.lo & MSR_PPIN_CAP) == 0) { - printk(BIOS_ERR, "MSR_PPIN_CAP is 0, PPIN is not supported\n"); - return ppin; - } - - /* Access to MSR_PPIN is permitted only if MSR_PPIN_CTL LOCK is 0 and ENABLE is 1 */ - msr = rdmsr(MSR_PPIN_CTL); - if (msr.lo & MSR_PPIN_CTL_LOCK) { - printk(BIOS_ERR, "MSR_PPIN_CTL_LOCK is 1, PPIN access is not allowed\n"); - return ppin; - } - - if ((msr.lo & MSR_PPIN_CTL_ENABLE) == 0) { - /* Set MSR_PPIN_CTL ENABLE to 1 */ - msr.lo |= MSR_PPIN_CTL_ENABLE; - wrmsr(MSR_PPIN_CTL, msr); - } - ppin = rdmsr(MSR_PPIN); - /* Set enable to 0 after reading MSR_PPIN */ - msr.lo &= ~MSR_PPIN_CTL_ENABLE; - wrmsr(MSR_PPIN_CTL, msr); - return ppin; -} -- cgit v1.2.3