From d2718c93815ab18bc65b866dff42d1e625fe5f2c Mon Sep 17 00:00:00 2001 From: Jonathan Zhang Date: Fri, 17 Jul 2020 17:35:12 -0700 Subject: soc/intel/xeon_sp/cpx: add VT-d support Intel CPX-SP FSP added support for VT-d through adding UPD parameter X2apic. Based on devicetree.cb setting, enable VT-d programming through FSP-M. When VT-d is enabled, add DMAR ACPI table. Signed-off-by: Jonathan Zhang Change-Id: Ic66374af6e53fb847c1bdc324eb3f4e01c334a94 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44280 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Maxim Polyakov --- src/soc/intel/xeon_sp/cpx/chip.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'src/soc/intel/xeon_sp/cpx/chip.h') diff --git a/src/soc/intel/xeon_sp/cpx/chip.h b/src/soc/intel/xeon_sp/cpx/chip.h index aa605a4aad..434b343bb2 100644 --- a/src/soc/intel/xeon_sp/cpx/chip.h +++ b/src/soc/intel/xeon_sp/cpx/chip.h @@ -84,6 +84,9 @@ struct soc_intel_xeon_sp_cpx_config { uint32_t pstate_req_ratio; + uint8_t vtd_support; + uint8_t x2apic; + /* Generic IO decode ranges */ uint32_t gen1_dec; uint32_t gen2_dec; -- cgit v1.2.3