From 2e410757efb824555191d8afd78cf79ab5ba6049 Mon Sep 17 00:00:00 2001 From: Andrey Petrov Date: Fri, 20 Mar 2020 12:08:32 -0700 Subject: soc/intel/xeon_sp: Add basic Cooperlake-SP support This adds barebones support. What works: * Linux kernel boots fine * SIRQ and PCH interupts work fine (only in IOAPIC mode) * PCH devices are usable What doesn't: * MP init is not there yet, only 1 CPU is up * SMM is not supported * GPIO is not available * All IIO and extended bus numbers enumeration is not yet available * Warm reset flow is untested * MRC cache save/load TEST=boots into Linux Signed-off-by: Andrey Petrov Change-Id: I7c987badc3c53f16ad178369c7e0906d6596e465 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39713 Reviewed-by: Maxim Polyakov Tested-by: build bot (Jenkins) --- src/soc/intel/xeon_sp/cpx/chip.h | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) create mode 100644 src/soc/intel/xeon_sp/cpx/chip.h (limited to 'src/soc/intel/xeon_sp/cpx/chip.h') diff --git a/src/soc/intel/xeon_sp/cpx/chip.h b/src/soc/intel/xeon_sp/cpx/chip.h new file mode 100644 index 0000000000..d86b8e7efa --- /dev/null +++ b/src/soc/intel/xeon_sp/cpx/chip.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#ifndef _SOC_CHIP_H_ +#define _SOC_CHIP_H_ + +#include +#include + +struct soc_intel_xeon_sp_cpx_config { + /* Common struct containing soc config data required by common code */ + struct soc_intel_common_config common_soc_config; + + /* Generic IO decode ranges */ + uint32_t gen1_dec; + uint32_t gen2_dec; + uint32_t gen3_dec; + uint32_t gen4_dec; +}; + +extern struct chip_operations soc_intel_xeon_sp_cpx_ops; + +typedef struct soc_intel_xeon_sp_cpx_config config_t; + +#endif -- cgit v1.2.3