From ea198585628ea58a90d85957b7b87b8fd46b0176 Mon Sep 17 00:00:00 2001 From: Martin Roth Date: Thu, 18 Jan 2024 12:37:22 -0700 Subject: soc/intel: Rename Makefiles from .inc to .mk MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The .inc suffix is confusing to various tools as it's not specific to Makefiles. This means that editors don't recognize the files, and don't open them with highlighting and any other specific editor functionality. This issue is also seen in the release notes generation script where Makefiles get renamed before running cloc. Signed-off-by: Martin Roth Change-Id: Ib479b93b7d0b2e790d0495b6a6b4b4298a515d9a Reviewed-on: https://review.coreboot.org/c/coreboot/+/80073 Reviewed-by: Arthur Heymans Reviewed-by: Michael Niewöhner Reviewed-by: Felix Singer Reviewed-by: Maximilian Brune Tested-by: build bot (Jenkins) --- src/soc/intel/xeon_sp/cpx/Makefile.mk | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) create mode 100644 src/soc/intel/xeon_sp/cpx/Makefile.mk (limited to 'src/soc/intel/xeon_sp/cpx/Makefile.mk') diff --git a/src/soc/intel/xeon_sp/cpx/Makefile.mk b/src/soc/intel/xeon_sp/cpx/Makefile.mk new file mode 100644 index 0000000000..745e032137 --- /dev/null +++ b/src/soc/intel/xeon_sp/cpx/Makefile.mk @@ -0,0 +1,22 @@ +## SPDX-License-Identifier: GPL-2.0-only + +ifeq ($(CONFIG_SOC_INTEL_COOPERLAKE_SP),y) + +subdirs-y += ../../../../cpu/intel/turbo +subdirs-y += ../../../../cpu/intel/microcode + +romstage-y += romstage.c ddr.c soc_util.c +romstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c +romstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c + +ramstage-y += chip.c cpu.c soc_util.c soc_acpi.c +ramstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c +ramstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c +smm-$(CONFIG_HAVE_SMI_HANDLER) += soc_smihandler_util.c + +CPPFLAGS_common += -I$(src)/soc/intel/xeon_sp/cpx/include -I$(src)/soc/intel/xeon_sp/cpx +CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp2_0/cooperlake_sp + +cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-55-0b + +endif ## CONFIG_SOC_INTEL_COOPERLAKE_SP -- cgit v1.2.3