From ed624c71582ff420362b95c8da52c303b446428d Mon Sep 17 00:00:00 2001 From: Jonathan Zhang Date: Tue, 12 May 2020 15:58:45 -0700 Subject: soc/intel/xeon_sp/cpx: display UPDs and CPX-SP specific HOBs Support display of CPX-SP specific HOBs (when CONFIG_DISPLAY_HOBS is selected, and UPD parameters (when CONFIG_DISPLAY_UPD_DATA is selected). Such display is used for FSP debugging purpose. It adds small amount of boot time. Some UPD display log excerpts: UPD values for SiliconInit: 0x04: BifurcationPcie0 0x03: BifurcationPcie1 Some HOB display log excerpts: === FSP HOBs === 0x758df000: hob_list_ptr 0x758df000, 0x00000038 bytes: HOB_TYPE_HANDOFF 0x758df038, 0x00000028 bytes: HOB_TYPE_MEMORY_POOL Signed-off-by: Jonathan Zhang Signed-off-by: Reddy Chagam Change-Id: I42dd519103cc604d4cfee858f4774bd73c979e77 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41348 Reviewed-by: Philipp Deppenwiese Tested-by: build bot (Jenkins) --- src/soc/intel/xeon_sp/cpx/Makefile.inc | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'src/soc/intel/xeon_sp/cpx/Makefile.inc') diff --git a/src/soc/intel/xeon_sp/cpx/Makefile.inc b/src/soc/intel/xeon_sp/cpx/Makefile.inc index aca8572ed9..a7ac5d7964 100644 --- a/src/soc/intel/xeon_sp/cpx/Makefile.inc +++ b/src/soc/intel/xeon_sp/cpx/Makefile.inc @@ -9,7 +9,11 @@ subdirs-y += ../../../../cpu/x86/tsc subdirs-y += ../../../../cpu/intel/microcode romstage-y += romstage.c +romstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c + ramstage-y += chip.c acpi.c cpu.c soc_util.c +ramstage-$(CONFIG_DISPLAY_HOB) += hob_display.c +ramstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c CPPFLAGS_common += -I$(src)/soc/intel/xeon_sp/cpx/include -I$(src)/soc/intel/xeon_sp/cpx -- cgit v1.2.3